crypto/krb5/src/lib/crypto/builtin/sha2/sha256.c

124

uint32_t AA, BB, CC, DD, EE, FF, GG, HH;

crypto/krb5/src/lib/crypto/builtin/sha2/sha256.c

130

CC = C;

crypto/krb5/src/lib/crypto/builtin/sha2/sha256.c

147

T2 = Sigma0(AA) + Maj(AA,BB,CC);

crypto/krb5/src/lib/crypto/builtin/sha2/sha256.c

153

DD = CC;

crypto/krb5/src/lib/crypto/builtin/sha2/sha256.c

154

CC = BB;

crypto/krb5/src/lib/crypto/builtin/sha2/sha256.c

161

C += CC;

crypto/krb5/src/lib/crypto/builtin/sha2/sha512.c

132

uint64_t AA, BB, CC, DD, EE, FF, GG, HH;

crypto/krb5/src/lib/crypto/builtin/sha2/sha512.c

138

CC = C;

crypto/krb5/src/lib/crypto/builtin/sha2/sha512.c

155

T2 = Sigma0(AA) + Maj(AA,BB,CC);

crypto/krb5/src/lib/crypto/builtin/sha2/sha512.c

161

DD = CC;

crypto/krb5/src/lib/crypto/builtin/sha2/sha512.c

162

CC = BB;

crypto/krb5/src/lib/crypto/builtin/sha2/sha512.c

169

C += CC;

crypto/krb5/src/windows/installer/wix/custom/custom.cpp

12

CC = cl /nologo

crypto/krb5/src/windows/installer/wix/custom/custom.cpp

34

$(CC) /c /Fo$@ custom.cpp

sys/arm/nvidia/tegra_pinmux.c

214

GMUX(0x06C, CC, 5, clk2_req_pcc5, dap, rsvd2, rsvd3, rsvd4),

sys/arm/nvidia/tegra_pinmux.c

279

GMUX(0x258, CC, 4, sdmmc4_clk_pcc4, sdmmc4, rsvd2, gmi, rsvd4),

sys/arm/nvidia/tegra_pinmux.c

289

GMUX(0x284, CC, 0, cam_mclk_pcc0, vi, vi_alt1, vi_alt3, sdmmc2),

sys/arm/nvidia/tegra_pinmux.c

290

GMUX(0x288, CC, 1, pcc1, i2s4, rsvd2, rsvd3, sdmmc2),

sys/arm/nvidia/tegra_pinmux.c

299

GMUX(0x2AC, CC, 2, pcc2, i2s4, rsvd2, sdmmc3, sdmmc2),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

349

GMUX(0x194, CC, 7, pcc7, rsvd0, rsvd1, rsvd2, rsvd3, -1, 0, 0, 0, 0),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

350

GMUX(0x198, CC, 0, hdmi_cec_pcc0, cec, rsvd1, rsvd2, rsvd3, 0xa24, 12, 5, 20, 5),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

351

GMUX(0x19c, CC, 1, hdmi_int_dp_hpd_pcc1, dp, rsvd1, rsvd2, rsvd3, 0xa28, 12, 5, 20, 5),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

352

GMUX(0x1a0, CC, 2, spdif_out_pcc2, spdif, rsvd1, rsvd2, rsvd3, 0xad0, 12, 5, 20, 5),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

353

GMUX(0x1a4, CC, 3, spdif_in_pcc3, spdif, rsvd1, rsvd2, rsvd3, 0xacc, 12, 5, 20, 5),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

354

GMUX(0x1a8, CC, 4, usb_vbus_en0_pcc4, usb, rsvd1, rsvd2, rsvd3, 0xb5c, 12, 5, 20, 5),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

355

GMUX(0x1ac, CC, 5, usb_vbus_en1_pcc5, usb, rsvd1, rsvd2, rsvd3, 0xb60, 12, 5, 20, 5),

sys/arm64/nvidia/tegra210/tegra210_pinmux.c

356

GMUX(0x1b0, CC, 6, dp_hpd0_pcc6, dp, rsvd1, rsvd2, rsvd3, 0x99c, 12, 5, 20, 5),

sys/dev/bhnd/bhnd_subr.c

141

BHND_CDESC(BCM, 4706_CC, CC, "ChipCommon I/O Controller"),

sys/dev/bhnd/bhnd_subr.c

179

BHND_DEVICE(BCM, CC, NULL, bhnd_chipc_clkctl_quirks),

sys/dev/bhnd/bhnd_subr.c

78

BHND_CDESC(BCM, CC, CC, "ChipCommon I/O Controller"),

sys/dev/bhnd/bhndb/bhndb_hwdata.c

117

BHNDB_CLASS_PRIO(CC, LOW,

sys/dev/bhnd/bhndb/bhndb_hwdata.c

179

BHNDB_CLASS_PRIO(CC, LOW,

sys/dev/bhnd/cores/chipc/chipc.c

73

BHND_DEVICE(BCM, CC, NULL, chipc_quirks),

sys/dev/bhnd/cores/chipc/chipc_gpio.c

88

BHND_DEVICE(BCM, CC, "Broadcom ChipCommon GPIO", chipc_gpio_quirks),

sys/dev/bhnd/cores/chipc/pwrctl/bhnd_pwrctl.c

70

BHND_DEVICE(BCM, CC, "ChipCommon Power Control", pwrctl_quirks),

usr.bin/c89/c89.c

75

Argv.a[Argc++] = CC;

usr.bin/c89/c89.c

97

(void)execv(CC, Argv.b);

usr.bin/c89/c89.c

98

err(1, "execv(" CC ")");