sys/arm/allwinner/a10/a10_intc.c

120

aintc_write_4(sc, SW_INT_IRQ_PENDING_REG(0),

sys/arm/allwinner/a10/a10_intc.c

136

aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);

sys/arm/allwinner/a10/a10_intc.c

140

aintc_write_4(sc, SW_INT_MASK_REG(block), value);

sys/arm/allwinner/a10/a10_intc.c

155

aintc_write_4(sc, SW_INT_ENABLE_REG(block), value);

sys/arm/allwinner/a10/a10_intc.c

159

aintc_write_4(sc, SW_INT_MASK_REG(block), value);

sys/arm/allwinner/a10/a10_intc.c

343

aintc_write_4(sc, SW_INT_ENABLE_REG(i), 0);

sys/arm/allwinner/a10/a10_intc.c

344

aintc_write_4(sc, SW_INT_MASK_REG(i), 0xffffffff);

sys/arm/allwinner/a10/a10_intc.c

347

aintc_write_4(sc, SW_INT_PROTECTION_REG, 0x01);

sys/arm/allwinner/a10/a10_intc.c

350

aintc_write_4(sc, SW_INT_NMI_CTRL_REG, 0x00);

sys/arm/ti/aintc.c

102

aintc_write_4(sc, INTC_CONTROL, 1);

sys/arm/ti/aintc.c

109

aintc_write_4(sc, INTC_MIR_SET(irq >> 5), (1UL << (irq & 0x1F)));

sys/arm/ti/aintc.c

116

aintc_write_4(sc, INTC_MIR_CLEAR(irq >> 5), (1UL << (irq & 0x1F)));

sys/arm/ti/aintc.c

270

aintc_write_4(sc, INTC_SYSCONFIG, 2);

sys/arm/ti/aintc.c

276

aintc_write_4(sc, INTC_THRESHOLD, 0xFF);