CAS_WRITE_4
CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_LO,
CAS_WRITE_4(sc, CAS_RX_COMP_BASE_HI,
CAS_WRITE_4(sc, CAS_RX_COMP_BASE_LO,
CAS_WRITE_4(sc, CAS_RX_DESC_BASE_HI,
CAS_WRITE_4(sc, CAS_RX_DESC_BASE_LO,
CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_HI,
CAS_WRITE_4(sc, CAS_RX_DESC2_BASE_LO,
CAS_WRITE_4(sc, CAS_CAW, CAS_CAW_RR_DIS);
CAS_WRITE_4(sc, CAS_INF_BURST,
CAS_WRITE_4(sc, CAS_INTMASK,
CAS_WRITE_4(sc, CAS_CLEAR_ALIAS, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_MASK, ~CAS_MAC_RX_OVERFLOW);
CAS_WRITE_4(sc, CAS_MAC_TX_MASK,
CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
CAS_WRITE_4(sc, CAS_MAC_CTRL_MASK,
CAS_WRITE_4(sc, CAS_ERROR_MASK,
CAS_WRITE_4(sc, CAS_BIM_CONF,
CAS_WRITE_4(sc, CAS_TX_CONF, v | CAS_TX_CONF_TXDMA_EN |
CAS_WRITE_4(sc, CAS_RX_CONF,
CAS_WRITE_4(sc, CAS_RX_PTHRS,
CAS_WRITE_4(sc, CAS_RX_BLANK,
CAS_WRITE_4(sc, CAS_RX_AEMPTY_THRS,
CAS_WRITE_4(sc, CAS_RX_PSZ,
CAS_WRITE_4(sc, CAS_RX_RED, 0);
CAS_WRITE_4(sc, CAS_RX_REAS_DMA_ADDR, v);
CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_LO, 0);
CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_MD, 0);
CAS_WRITE_4(sc, CAS_RX_REAS_DMA_DATA_HI, 0);
CAS_WRITE_4(sc, CAS_RX_CTRL_FIFO, 0);
CAS_WRITE_4(sc, CAS_RX_IPP_ADDR, 0);
CAS_WRITE_4(sc, CAS_RX_CONF,
CAS_WRITE_4(sc, CAS_MAC_TX_CONF, v);
CAS_WRITE_4(sc, CAS_RX_KICK, CAS_NRXDESC - 4);
CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, 0);
CAS_WRITE_4(sc, CAS_RX_KICK2, CAS_NRXDESC2 - 4);
CAS_WRITE_4(sc, CAS_MAC_IPG0, 0);
CAS_WRITE_4(sc, CAS_MAC_IPG1, 8);
CAS_WRITE_4(sc, CAS_MAC_IPG2, 4);
CAS_WRITE_4(sc, CAS_MAC_MIN_FRAME, ETHER_MIN_LEN);
CAS_WRITE_4(sc, CAS_MAC_MAX_BF,
CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
CAS_WRITE_4(sc, CAS_MAC_JAM_SIZE, 0x4);
CAS_WRITE_4(sc, CAS_MAC_ATTEMPT_LIMIT, 0x10);
CAS_WRITE_4(sc, CAS_MAC_CTRL_TYPE, 0x8808);
CAS_WRITE_4(sc, CAS_MAC_RANDOM_SEED,
CAS_WRITE_4(sc, i, 0);
CAS_WRITE_4(sc, CAS_MAC_ADDR42, 0x0001);
CAS_WRITE_4(sc, CAS_MAC_ADDR43, 0xc200);
CAS_WRITE_4(sc, CAS_MAC_ADDR44, 0x0180);
CAS_WRITE_4(sc, CAS_MAC_AFILTER0, 0);
CAS_WRITE_4(sc, CAS_MAC_AFILTER1, 0);
CAS_WRITE_4(sc, CAS_MAC_AFILTER2, 0);
CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK1_2, 0);
CAS_WRITE_4(sc, CAS_MAC_AFILTER_MASK0, 0);
CAS_WRITE_4(sc, i, 0);
CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_DEFER_TMR_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_PEAK_ATTEMPTS, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_FRAME_COUNT, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
CAS_WRITE_4(sc, CAS_MAC_SPC, 0x1BF0 << CAS_MAC_SPC_TIME_SHFT);
CAS_WRITE_4(sc, CAS_MAC_ADDR0, (laddr[4] << 8) | laddr[5]);
CAS_WRITE_4(sc, CAS_MAC_ADDR1, (laddr[2] << 8) | laddr[3]);
CAS_WRITE_4(sc, CAS_MAC_ADDR2, (laddr[0] << 8) | laddr[1]);
CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, CAS_MAC_XIF_CONF_TX_OE);
CAS_WRITE_4(sc, CAS_TX_KICK3, sc->sc_txnext);
CAS_WRITE_4(sc, CAS_RX_COMP_TAIL, sc->sc_rxcptr);
CAS_WRITE_4(sc, CAS_RX_KICK,
CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
CAS_WRITE_4(sc, CAS_INTMASK,
CAS_WRITE_4(sc, CAS_MIF_CONF,
CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
CAS_WRITE_4(sc, CAS_PCS_CTRL, val);
CAS_WRITE_4(sc, CAS_PCS_CONF, 0);
CAS_WRITE_4(sc, CAS_PCS_ANAR, val);
CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL,
CAS_WRITE_4(sc, CAS_PCS_CONF,
CAS_WRITE_4(sc, reg, val);
CAS_WRITE_4(sc, CAS_MIF_FRAME, v);
CAS_WRITE_4(sc, CAS_MAC_TX_CONF, txcfg);
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, rxcfg);
CAS_WRITE_4(sc, CAS_MAC_CTRL_CONF, v);
CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x41);
CAS_WRITE_4(sc, CAS_MAC_PREAMBLE_LEN, 0x7);
CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
CAS_WRITE_4(sc, CAS_MAC_SLOT_TIME,
CAS_WRITE_4(sc, CAS_MAC_XIF_CONF, v);
CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v);
CAS_WRITE_4(sc,
CAS_WRITE_4(sc, CAS_MAC_RX_CONF, v | CAS_MAC_RX_CONF_EN);
CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN,
CAS_WRITE_4(sc, CAS_BIM_LDEV_OEN, 0);
CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_MII);
CAS_WRITE_4(sc, CAS_MIF_CONF, v);
CAS_WRITE_4(sc, CAS_SATURN_PCFG,
CAS_WRITE_4(sc, CAS_MIF_CONF, v);
CAS_WRITE_4(sc, CAS_SATURN_PCFG,
CAS_WRITE_4(sc, CAS_PCS_DATAPATH, CAS_PCS_DATAPATH_SERDES);
CAS_WRITE_4(sc, CAS_SATURN_PCFG, 0);
CAS_WRITE_4(sc, CAS_PCS_SERDES_CTRL, CAS_PCS_SERDES_CTRL_ESD);
CAS_WRITE_4(sc, CAS_PCS_CONF, CAS_PCS_CONF_EN);
CAS_WRITE_4(sc, CAS_MAC_NORM_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_FIRST_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_EXCESS_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_LATE_COLL_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_LEN_ERR_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_ALIGN_ERR, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_CRC_ERR_CNT, 0);
CAS_WRITE_4(sc, CAS_MAC_RX_CODE_VIOL, 0);
CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX | CAS_RESET_TX |
CAS_WRITE_4(sc, CAS_INTMASK, 0xffffffff);
CAS_WRITE_4(sc, CAS_RX_CONF, 0);
CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_RX |
CAS_WRITE_4(sc, CAS_TX_CONF, 0);
CAS_WRITE_4(sc, CAS_RESET, CAS_RESET_TX |
CAS_WRITE_4(sc, CAS_MAC_RX_CONF,
CAS_WRITE_4(sc, CAS_MAC_TX_CONF,
CAS_WRITE_4(sc, CAS_TX_DESC3_BASE_HI,