ADF_CSR_RD
ADF_CSR_RD((csr_base_addr), \
ADF_CSR_RD((csr_base_addr), \
ADF_CSR_RD((csr_base_addr), \
ADF_CSR_RD((csr_base_addr), \
l_base = ADF_CSR_RD(csr_base_addr,
u_base = ADF_CSR_RD(csr_base_addr,
unsigned int val = ADF_CSR_RD(csr, offs);
unsigned int val = ADF_CSR_RD(csr, offs);
ADF_CSR_RD(pmisc_bar_addr, \
ADF_CSR_RD(pmisc_bar_addr, \
ADF_CSR_RD(csr_addr, \
ADF_CSR_RD(csr_base_addr, \
ADF_CSR_RD(csr_base_addr, \
ADF_CSR_RD(csr_base_addr, \
l_base = ADF_CSR_RD(csr_base_addr,
u_base = ADF_CSR_RD(csr_base_addr,
ADF_CSR_RD((csr_base_addr), \
ADF_CSR_RD((csr_base_addr), \
ADF_CSR_RD((csr_base_addr), \
ADF_CSR_RD((csr_base_addr), \
l_base = ADF_CSR_RD(csr_base_addr,
u_base = ADF_CSR_RD(csr_base_addr,
l_base = ADF_CSR_RD(csr_base_addr,
u_base = ADF_CSR_RD(csr_base_addr,
ADF_CSR_RD(csr_base_addr, \
ADF_CSR_RD(csr_base_addr, \
ADF_CSR_RD(csr_base_addr, \
ADF_CSR_RD(handle->hal_misc_addr_v, CAP_CSR_ADDR(csr))
ADF_CSR_RD(handle->hal_misc_addr_v, AE_CSR_ADDR(handle, ae, csr))
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMPAD(dev, 2));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMPAD(dev, 3));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMPAD(dev, 4));
val = ADF_CSR_RD(csr, adf_err_regs[i].offs);
u32 slice_hang = ADF_CSR_RD(csr, slice_hang_offset);
u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3);
u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5);
if (ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num)) &
return ADF_CSR_RD(pmisc_bar_addr, ADF_INTSTATSSM(dev));
return ADF_CSR_RD(pmisc_bar_addr, ADF_PPERR(dev));
return ADF_CSR_RD(pmisc_bar_addr, ADF_PPERRID(dev));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMSH(dev));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMSHAD(dev));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMP(dev, 0));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMP(dev, 1));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMP(dev, 2));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMP(dev, 3));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMP(dev, 4));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMPAD(dev, 0));
return ADF_CSR_RD(pmisc_bar_addr, ADF_UERRSSMMMPAD(dev, 1));
if (ADF_CSR_RD(mailbox, mb_offset) == 1) {
if (ADF_CSR_RD(mailbox, mb_offset) == 0) {
val = ADF_CSR_RD(csr, ADF_WQM_CSR_RPRESETSTS(bank_number));
ret = read_poll_timeout(ADF_CSR_RD,
csr_val = ADF_CSR_RD(pmisc_addr, pfvf_offset);
ADF_CSR_RD(csr_addr, \
errsou3 = ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU3);
errsou5 = ADF_CSR_RD(pmisc_bar_addr, ADF_ERRSOU5);
csr_val = ADF_CSR_RD(handle->hal_misc_addr_v, csr_addr);
csr_val = ADF_CSR_RD(handle->hal_misc_addr_v, csr_addr);
csr_val = ADF_CSR_RD(handle->hal_misc_addr_v, csr_addr);
u32 errsou0 = ADF_CSR_RD(csr, ADF_ERRSOU0) & ADF_200XX_ERRMSK0_UERR;
u32 errsou1 = ADF_CSR_RD(csr, ADF_ERRSOU1) & ADF_200XX_ERRMSK1_UERR;
u32 errsou3 = ADF_CSR_RD(csr, ADF_ERRSOU3) & ADF_200XX_ERRMSK3_UERR;
u32 errsou5 = ADF_CSR_RD(csr, ADF_ERRSOU5) & ADF_200XX_ERRMSK5_UERR;
val = ADF_CSR_RD(csr, ADF_200XX_AE_CTX_ENABLES(i));
val = ADF_CSR_RD(csr, ADF_200XX_AE_MISC_CONTROL(i));
val = ADF_CSR_RD(csr, ADF_200XX_UERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_200XX_CERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_PPERR(i));
csr = ADF_CSR_RD(addr, ADF_4XXX_ERRMSK2);
ret = read_poll_timeout(ADF_CSR_RD,
v_sou = ADF_CSR_RD(pmisc_bar_addr, ADF_4XXXIOV_VINTSOUPF2VM_OFFSET);
v_msk = ADF_CSR_RD(pmisc_bar_addr, ADF_4XXXIOV_VINTMSKPF2VM_OFFSET);
v_sou = ADF_CSR_RD(pmisc_bar_addr, ADF_4XXXIOV_VINTSOU_OFFSET);
v_msk = ADF_CSR_RD(pmisc_bar_addr, ADF_4XXXIOV_VINTMSK_OFFSET);
val = ADF_CSR_RD(csr, ADF_C3XXX_AE_CTX_ENABLES(i));
val = ADF_CSR_RD(csr, ADF_C3XXX_AE_MISC_CONTROL(i));
val = ADF_CSR_RD(csr, ADF_C3XXX_UERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_C3XXX_CERRSSMSH(i));
sa_db_ctl_value = ADF_CSR_RD(aram_csr_base, ADF_C4XXX_REG_SA_DB_CTRL);
reg = ADF_CSR_RD(addr + ADF_C4XXX_AE2FUNC_MAP_OFFSET,
u32 errsou10 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU10);
fw_irq_source = ADF_CSR_RD(csr, ADF_INTSTATSSM(accel_num));
ADF_CSR_RD(csr, ADF_C4XXX_IAINTSTATSSM(accel_num));
u32 errsou11 = ADF_CSR_RD(csr, ADF_C4XXX_ERRSOU11);
u32 doorbell_int = ADF_CSR_RD(csr, ADF_C4XXX_ETH_DOORBELL_INT);
eth_doorbell_reg[i] = ADF_CSR_RD(csr, data_reg);
val = ADF_CSR_RD(csr, ADF_C4XXX_AE_CTX_ENABLES(i));
val = ADF_CSR_RD(csr, ADF_C4XXX_AE_MISC_CONTROL(i));
val = ADF_CSR_RD(csr, ADF_C4XXX_UERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_C4XXX_CERRSSMSH(i));
ADF_CSR_RD(csr_addr, (csr_offset) + ((index)*ADF_C4XXX_WQM_SIZE))
reg_val = ADF_CSR_RD(aram_base_addr, rf_par_addr + offset);
reg_val = ADF_CSR_RD(aram_base_addr,
errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU8);
errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU9);
errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU10);
errsou = ADF_CSR_RD(pmisc, ADF_C4XXX_ERRSOU11);
u32 mecorrerr = ADF_CSR_RD(pmisc, ADF_C4XXX_HI_ME_COR_ERRLOG);
u32 me_uncorr_err = ADF_CSR_RD(pmisc, ADF_C4XXX_HI_ME_UNCERR_LOG);
ri_mem_par_err_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_MEM_PAR_ERR_STS);
ri_mem_par_err_ferr = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_MEM_PAR_ERR_FERR);
ti_mem_par_err_sts0 = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_STS0);
ti_mem_par_err_sts1 = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_STS1);
ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MEM_PAR_ERR_FIRST_ERROR);
ADF_CSR_RD(pmisc, ADF_C4XXX_HI_CPP_AGENT_CMD_PAR_ERR_LOG);
exprpssmcpr = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMCPR0(accel));
exprpssmcpr = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMCPR1(accel));
exprpssmxlt = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMXLT0(accel));
exprpssmxlt = ADF_CSR_RD(pmisc, ADF_C4XXX_EXPRPSSMXLT1(accel));
u32 statssm = ADF_CSR_RD(pmisc, ADF_INTSTATSSM(accel));
u32 iastatssm = ADF_CSR_RD(pmisc, ADF_C4XXX_IAINTSTATSSM(accel));
ti_misc_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_MISC_STS);
ri_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_CPP_INT_STS);
ti_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_CPP_INT_STS);
aram_cerr = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_ARAMCERR);
aram_uerr = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_ARAMUERR);
ti_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_TI_CPP_INT_STS);
ri_cpp_int_sts = ADF_CSR_RD(pmisc, ADF_C4XXX_RI_CPP_INT_STS);
reg_val = ADF_CSR_RD(aram_base_addr, ADF_C4XXX_IC_PARSER_UERR + offset);
val = ADF_CSR_RD(csr, ADF_C62X_AE_CTX_ENABLES(i));
val = ADF_CSR_RD(csr, ADF_C62X_AE_MISC_CONTROL(i));
val = ADF_CSR_RD(csr, ADF_C62X_UERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_C62X_CERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_CTX_ENABLES(i));
val = ADF_CSR_RD(csr, ADF_DH895XCC_AE_MISC_CONTROL(i));
val = ADF_CSR_RD(csr, ADF_DH895XCC_UERRSSMSH(i));
val = ADF_CSR_RD(csr, ADF_DH895XCC_CERRSSMSH(i));