__u64
__u64 cq_va;
__u64 cq_handle;
__u64 dbr;
__u64 uctx_cq_page;
__u64 cq_va;
__u64 qpsva;
__u64 qprva;
__u64 qp_handle;
__u64 comp_mask;
__u64 srqva;
__u64 srq_handle;
__u64 dbr;
__u64 comp_mask;
__u64 dbr_bar_addr;
#define V_PPOD_TID(x) ((__u64)(x) << S_PPOD_TID)
#define V_PPOD_VALID(x) ((__u64)(x) << S_PPOD_VALID)
#define V_PPOD_LEN(x) ((__u64)(x) << S_PPOD_LEN)
#define V_SGE_TIMESTAMP(x) ((__u64)(x) << S_SGE_TIMESTAMP)
#define G_SGE_TIMESTAMP(x) (((__u64)(x) >> S_SGE_TIMESTAMP) & M_SGE_TIMESTAMP)
#define V_TXPKT_IPHDR_LEN(x) ((__u64)(x) << S_TXPKT_IPHDR_LEN)
#define V_TXPKT_CSUM_LOC(x) ((__u64)(x) << S_TXPKT_CSUM_LOC)
#define V_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_TXPKT_ETHHDR_LEN)
#define V_T6_TXPKT_ETHHDR_LEN(x) ((__u64)(x) << S_T6_TXPKT_ETHHDR_LEN)
#define V_TXPKT_CSUM_TYPE(x) ((__u64)(x) << S_TXPKT_CSUM_TYPE)
#define V_TXPKT_VLAN(x) ((__u64)(x) << S_TXPKT_VLAN)
#define V_TXPKT_VLAN_VLD(x) ((__u64)(x) << S_TXPKT_VLAN_VLD)
#define V_TXPKT_IPSEC(x) ((__u64)(x) << S_TXPKT_IPSEC)
#define V_TXPKT_IPCSUM_DIS(x) ((__u64)(x) << S_TXPKT_IPCSUM_DIS)
#define V_TXPKT_L4CSUM_DIS(x) ((__u64)(x) << S_TXPKT_L4CSUM_DIS)
#define V_WR_OP(x) ((__u64)(x) << S_WR_OP)
__u64 cookie;
#define V_SMAC_SEL(x) ((__u64)(x) << S_SMAC_SEL)
#define V_L2T_IDX(x) ((__u64)(x) << S_L2T_IDX)
#define V_TCAM_BYPASS(x) ((__u64)(x) << S_TCAM_BYPASS)
#define V_NAGLE(x) ((__u64)(x) << S_NAGLE)
#define V_WND_SCALE(x) ((__u64)(x) << S_WND_SCALE)
#define V_KEEP_ALIVE(x) ((__u64)(x) << S_KEEP_ALIVE)
#define V_MAX_RT(x) ((__u64)(x) << S_MAX_RT)
#define V_MAX_RT_OVERRIDE(x) ((__u64)(x) << S_MAX_RT_OVERRIDE)
#define V_MSS_IDX(x) ((__u64)(x) << S_MSS_IDX)
#define V_TCB_SND_NXT_RAW(x) ((__u64)(x) << S_TCB_SND_NXT_RAW)
#define V_TCB_SND_MAX_RAW(x) ((__u64)(x) << S_TCB_SND_MAX_RAW)
#define V_TCB_SND_REC_RAW(x) ((__u64)(x) << S_TCB_SND_REC_RAW)
#define V_TCB_SND_CWND(x) ((__u64)(x) << S_TCB_SND_CWND)
#define V_TCB_SND_SSTHRESH(x) ((__u64)(x) << S_TCB_SND_SSTHRESH)
#define V_TCB_TX_LAST_PTR_RAW(x) ((__u64)(x) << S_TCB_TX_LAST_PTR_RAW)
#define V_TCB_RCV_NXT(x) ((__u64)(x) << S_TCB_RCV_NXT)
#define V_TCB_RCV_WND(x) ((__u64)(x) << S_TCB_RCV_WND)
#define V_TCB_RX_HDR_OFFSET(x) ((__u64)(x) << S_TCB_RX_HDR_OFFSET)
#define V_TCB_RX_FRAG0_START_IDX_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG0_START_IDX_RAW)
#define V_TCB_RX_FRAG1_START_IDX_OFFSET(x) ((__u64)(x) << S_TCB_RX_FRAG1_START_IDX_OFFSET)
#define V_TCB_RX_FRAG0_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG0_LEN)
#define V_TCB_RX_FRAG1_LEN(x) ((__u64)(x) << S_TCB_RX_FRAG1_LEN)
#define V_TCB_RX_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_PTR_RAW)
#define V_TCB_RX_FRAG2_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_START_IDX_OFFSET_RAW)
#define V_TCB_RX_FRAG2_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG2_LEN_RAW)
#define V_TCB_RX_FRAG3_PTR_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_PTR_RAW)
#define V_TCB_RX_FRAG3_LEN_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_LEN_RAW)
#define V_TCB_RX_FRAG3_START_IDX_OFFSET_RAW(x) ((__u64)(x) << S_TCB_RX_FRAG3_START_IDX_OFFSET_RAW)
#define V_TCB_RQ_MSN(x) ((__u64)(x) << S_TCB_RQ_MSN)
#define V_TCB_RX_DDP_BUF0_LEN(x) ((__u64)(x) << S_TCB_RX_DDP_BUF0_LEN)
#define V_TCB_RX_DDP_FLAGS(x) ((__u64)(x) << S_TCB_RX_DDP_FLAGS)
#define V_TCB_RX_TLS_BUF_LEN(x) ((__u64)(x) << S_TCB_RX_TLS_BUF_LEN)
#define V_TCB_RX_TLS_FLAGS(x) ((__u64)(x) << S_TCB_RX_TLS_FLAGS)
#define V_TCB_RX_TLS_SEQ(x) ((__u64)(x) << S_TCB_RX_TLS_SEQ)
#define V_TCB_T_FLAGS(x) ((__u64)(x) << S_TCB_T_FLAGS)
#define V_TCB_N_RQ_MSN(x) ((__u64)(x) << S_TCB_N_RQ_MSN)
#define V_TF_RCV_COALESCE_HEARTBEAT(x) ((__u64)(x) << S_TF_RCV_COALESCE_HEARTBEAT)
#define V_TF_RSS_FW(x) ((__u64)(x) << S_TF_RSS_FW)
#define V_TF_ACTIVE_OPEN(x) ((__u64)(x) << S_TF_ACTIVE_OPEN)
#define V_TF_ASK_MODE(x) ((__u64)(x) << S_TF_ASK_MODE)
#define V_TF_MOD_SCHD_REASON0(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON0)
#define V_TF_MOD_SCHD_REASON1(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON1)
#define V_TF_MOD_SCHD_REASON2(x) ((__u64)(x) << S_TF_MOD_SCHD_REASON2)
#define V_TF_MOD_SCHD_TX(x) ((__u64)(x) << S_TF_MOD_SCHD_TX)
#define V_TF_MOD_SCHD_RX(x) ((__u64)(x) << S_TF_MOD_SCHD_RX)
#define V_TF_TIMER(x) ((__u64)(x) << S_TF_TIMER)
#define V_TF_DACK_TIMER(x) ((__u64)(x) << S_TF_DACK_TIMER)
#define V_TF_PEER_FIN(x) ((__u64)(x) << S_TF_PEER_FIN)
#define V_TF_TX_COMPACT(x) ((__u64)(x) << S_TF_TX_COMPACT)
#define V_TF_RX_COMPACT(x) ((__u64)(x) << S_TF_RX_COMPACT)
#define V_TF_RDMA_ERROR(x) ((__u64)(x) << S_TF_RDMA_ERROR)
#define V_TF_RDMA_FLM_ERROR(x) ((__u64)(x) << S_TF_RDMA_FLM_ERROR)
#define V_TF_TX_PDU_OUT(x) ((__u64)(x) << S_TF_TX_PDU_OUT)
#define V_TF_RX_PDU_OUT(x) ((__u64)(x) << S_TF_RX_PDU_OUT)
#define V_TF_DUPACK_COUNT_ODD(x) ((__u64)(x) << S_TF_DUPACK_COUNT_ODD)
#define V_TF_FAST_RECOVERY(x) ((__u64)(x) << S_TF_FAST_RECOVERY)
#define V_TF_RECV_SCALE(x) ((__u64)(x) << S_TF_RECV_SCALE)
#define V_TF_NAT_FLAG_CHECK(x) ((__u64)(x) << S_TF_NAT_FLAG_CHECK)
#define V_TF_RECV_TSTMP(x) ((__u64)(x) << S_TF_RECV_TSTMP)
#define V_TF_LPBK_TX_LPBK(x) ((__u64)(x) << S_TF_LPBK_TX_LPBK)
#define V_TF_RECV_SACK(x) ((__u64)(x) << S_TF_RECV_SACK)
#define V_TF_SWAP_MAC_ADDR(x) ((__u64)(x) << S_TF_SWAP_MAC_ADDR)
#define V_TF_PEND_CTL0(x) ((__u64)(x) << S_TF_PEND_CTL0)
#define V_TF_PEND_CTL1(x) ((__u64)(x) << S_TF_PEND_CTL1)
#define V_TF_PEND_CTL2(x) ((__u64)(x) << S_TF_PEND_CTL2)
#define V_TF_IP_VERSION(x) ((__u64)(x) << S_TF_IP_VERSION)
#define V_TF_CCTRL_ECN(x) ((__u64)(x) << S_TF_CCTRL_ECN)
#define V_TF_LPBK(x) ((__u64)(x) << S_TF_LPBK)
#define V_TF_CCTRL_ECE(x) ((__u64)(x) << S_TF_CCTRL_ECE)
#define V_TF_REWRITE_DMAC(x) ((__u64)(x) << S_TF_REWRITE_DMAC)
#define V_TF_CCTRL_CWR(x) ((__u64)(x) << S_TF_CCTRL_CWR)
#define V_TF_REWRITE_SMAC(x) ((__u64)(x) << S_TF_REWRITE_SMAC)
#define V_TF_CCTRL_RFR(x) ((__u64)(x) << S_TF_CCTRL_RFR)
#define V_TF_INSERT_VLAN(x) ((__u64)(x) << S_TF_INSERT_VLAN)
#define V_TF_CORE_BYPASS(x) ((__u64)(x) << S_TF_CORE_BYPASS)
#define V_TF_DDP_BUF1_VALID(x) ((__u64)(x) << S_TF_DDP_BUF1_VALID)
#define V_TF_DDP_BUF1_INDICATE(x) ((__u64)(x) << S_TF_DDP_BUF1_INDICATE)
#define V_TF_DDP_BUF1_FLUSH(x) ((__u64)(x) << S_TF_DDP_BUF1_FLUSH)
#define V_TF_DDP_PSHF_ENABLE_1(x) ((__u64)(x) << S_TF_DDP_PSHF_ENABLE_1)
#define V_TF_DDP_PUSH_DISABLE_1(x) ((__u64)(x) << S_TF_DDP_PUSH_DISABLE_1)
#define V_TF_DDP_PSH_NO_INVALIDATE1(x) ((__u64)(x) << S_TF_DDP_PSH_NO_INVALIDATE1)
__u64 imm_data;
__u64 cookie;
__u64 cookie;
__u64 immd_data;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 cookie;
__u64 key;
__u64 gts_key;
__u64 memsize;
__u64 ma_sync_key;
__u64 sq_key;
__u64 rq_key;
__u64 sq_db_gts_key;
__u64 rq_db_gts_key;
__u64 sq_memsize;
__u64 rq_memsize;
__u64 status_page_key;
__u64 size;
__u64 capability;
__u64 value;
__u64 user_data;
__u64 crtc_id_ptr;
__u64 connector_id_ptr;
__u64 encoder_id_ptr;
__u64 set_connectors_ptr;
__u64 format_type_ptr;
__u64 plane_id_ptr;
__u64 encoders_ptr;
__u64 modes_ptr;
__u64 props_ptr;
__u64 prop_values_ptr;
__u64 value;
__u64 values_ptr; /* values and blob lengths */
__u64 enum_blob_ptr; /* enum and blob id ptrs */
__u64 value;
__u64 props_ptr;
__u64 prop_values_ptr;
__u64 value;
__u64 data;
__u64 clips_ptr;
__u64 red;
__u64 green;
__u64 blue;
__u64 user_data;
__u64 offset;
__u64 fb_id_ptr;
__u64 hca_core_clock_offset;
__u64 requests[IEEE_8021QAZ_MAX_TCS];
__u64 indications[IEEE_8021QAZ_MAX_TCS];
__u64 sq_db_page;
__u64 rq_db_page;
__u64 arm_db_page;
__u64 set_db_page;
__u64 db_page;
__u64 uid;
resp.node_guid = (__force __u64) ctx->cm_id->device->node_guid;
resp->node_guid = (__force __u64) cm_id->device->node_guid;
__u64 element, __u64 event, struct list_head *obj_list,
__u64 vaddr;
__u64 sib_scope_id;
__u64 offset;
__u64 response;
__u64 response;
__u64 data;
__u64 data;
__u64 primary_path;
__u64 alternate_path;
__u64 uid;
__u64 data;
__u64 info;
__u64 data;
__u64 data;
__u64 path;
__u64 data;
__u64 data;
__u64 path;
__u64 info;
__u64 data;
__u64 response;
__u64 data;
__u64 info;
__u64 uid;
__u64 uid;
__u64 response;
__u64 response;
__u64 data[0];
__u64 method_mask[2];
__u64 buf_addr;
__u64 db_addr;
__u64 buf_addr;
__u64 db_addr;
__u64 buf_addr;
__u64 buf_addr;
__u64 db_addr;
__u64 hca_core_clock_offset;
__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
__u64 buf_addr;
__u64 db_addr;
__u64 buf_addr;
__u64 buf_addr;
__u64 db_addr;
__u64 buf_addr;
__u64 db_addr;
__u64 sq_buf_addr;
__u64 rx_hash_fields_mask; /* enum mlx5_rx_hash_fields */
__u64 buf_addr;
__u64 db_addr;
MLX5_LIB_CAP_4K_UAR = (__u64)1 << 0,
MLX5_LIB_CAP_DYN_UAR = (__u64)1 << 1,
__u64 sq_db_page;
__u64 rq_db_page;
__u64 arm_db_page;
__u64 set_db_page;
__u64 db_page;
__u64 response;
__u64 response;
__u64 response;
__u64 node_guid;
__u64 node_guid;
__u64 uid;
__u64 response;
__u64 response; /* rdma_ucm_create_id_resp */
__u64 uid;
__u64 response; /* rdma_ucma_create_id_resp */
__u64 uid;
__u64 response;
__u64 uid;
__u64 optval;
__u64 response;
__u64 uid;
__u64 response;
req.aio_buf = (__u64)bufaddr;