__iomem
#define IOMEM_ERR_PTR(err) (void __iomem *)ERR_PTR(err)
int (*read_reg)(struct mhi_controller *, void __iomem *, uint32_t *);
void (*write_reg)(struct mhi_controller *, void __iomem *, uint32_t);
void __iomem **linuxkpi_pcim_iomap_table(struct pci_dev *pdev);
void __iomem **
struct unit_regs __iomem *regs_base =
(struct unit_regs __iomem *)adapter->udma_base;
struct al_iofic_grp_ctrl __iomem *sec_ints_base;
(struct unit_regs __iomem *)adapter->udma_base,
(struct unit_regs __iomem *)adapter->udma_base,
struct unit_regs __iomem *regs_base =
(struct unit_regs __iomem *)adapter->udma_base;
struct unit_regs __iomem *regs_base =
(struct unit_regs __iomem *)adapter->udma_base;
if (al_udma_iofic_config((struct unit_regs __iomem *)adapter->udma_base,
void __iomem *serdes_base;
void __iomem *bar0;
void __iomem *db;
mbox->prod = (void __iomem *)((char *)mbox->reg.bar_reg +
mbox->db = (void __iomem *)((char *)mbox->reg.bar_reg +
void __iomem *prod;
void __iomem *db;
void __iomem *db;
void __iomem *bar_reg;
void __iomem *db;
void __iomem *priv_db;
void __iomem *dbr;
void __iomem *priv_db;
u64 key, void __iomem *db,
static inline void __replay_writeq(u64 key, void __iomem *db)
cq->bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
iwsc->rdev.bar2_kva = (void __iomem *)((u64)iwsc->rdev.adap->udbs_base);
void __iomem *bar2_kva;
wq->sq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
wq->rq.bar2_va = (void __iomem *)((u64)rdev->bar2_kva +
void __iomem *bar2_va;
void __iomem *bar2_va;
static inline void pio_copy(u64 __iomem *dst, u64 *src)
pio_copy((u64 __iomem *)
(void __iomem *)((u64)wq->sq.bar2_va +
pio_copy((u64 __iomem *)((u64)wq->rq.bar2_va +
(void __iomem *)((u64)wq->rq.bar2_va +
void __iomem *bar2_va;
(void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS));
(void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS));
(void __iomem *)((u64)cq->bar2_va + SGE_UDB_GTS));
#ifndef __iomem
struct vnic_res __iomem *devcmd;
void __iomem *res;
void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
struct vnic_res __iomem *devcmd = vdev->devcmd;
struct vnic_resource_header __iomem *rh;
struct mgmt_barmap_hdr __iomem *mrh;
struct vnic_resource __iomem *r;
void __iomem *vaddr;
void __iomem *vaddr;
void __iomem *vnic_dev_get_res(struct vnic_dev *vdev, enum vnic_res_type type,
void __iomem *shm_base;
void __iomem *db_page_base;
void __iomem *addr;
void __iomem *ptr = (uint8_t *)base + SMC_LAST_DWORD * SMC_BASIC_UNIT;
void __iomem *base = sc->base;
mana_smc_init(struct shm_channel *sc, device_t dev, void __iomem *base)
mana_smc_poll_register(void __iomem *base, bool reset)
void __iomem *base;
void mana_smc_init(struct shm_channel *sc, device_t dev, void __iomem *base);
u8 __iomem *uar_page,
void __iomem *map;
void __iomem *bf_map;
void __iomem *reg;
static inline void mlx4_write64(__be32 val[2], void __iomem *dest,
static inline void mlx4_write64(__be32 val[2], void __iomem *dest,
void __iomem *doorbell;
struct mlx4_comm __iomem *comm;
void __iomem *hcr;
void __iomem *clr_int;
void __iomem **uar_map;
u32 __iomem *map;
void __iomem *clr_base;
void __iomem *kar;
void __iomem *clock_mapping;
comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
(__iomem char *)priv->mfunc.comm + MLX4_COMM_CHAN_FLAGS);
comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
u32 __iomem *hcr = cmd->hcr;
void __iomem *hcr = priv->cmd.hcr;
static void __iomem *mlx4_get_eq_uar(struct mlx4_dev *dev, struct mlx4_eq *eq)
comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
void __iomem *owner;
void __iomem *owner;
void __iomem *reset;
void __iomem *uar_map;
static void mlx4_bf_copy(void __iomem *dst, volatile unsigned long *src, unsigned bytecnt)
void __iomem *uar_map;
void __iomem *uar_page,
static inline void mlx5_write64(__be32 val[2], void __iomem *dest,
static inline void mlx5_write64(__be32 val[2], void __iomem *dest,
u32 __iomem *vector;
__be32 __iomem *doorbell;
void __iomem *map;
void __iomem *map;
void __iomem *update_ci;
void __iomem *update_arm_ci;
struct mlx5_health_buffer __iomem *health;
__be32 __iomem *health_counter;
struct mlx5_init_seg __iomem *iseg;
__be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2);
struct mlx5_health_buffer __iomem *h = health->health;
struct mlx5_health_buffer __iomem *h = health->health;
struct mlx5_health_buffer __iomem *h = health->health;
void __iomem *uar_map;
void __iomem *uar_map;
void __iomem *uar_page = mdev->priv.uar->map;
void __iomem *uar_map;
void __iomem *ptr = dev->cmd.dbell_map;
void __iomem *dbell_map;
void __iomem *mpt_base;
void __iomem *mtt_base;
void __iomem *clr_int;
void __iomem *av_map;
u32 __iomem *map;
void __iomem *hcr;
void __iomem *kar;
void __iomem *clr_base;
void __iomem *ecr_base;
void __iomem *eq_arm;
void __iomem *eq_set_ci_base;
static inline void mthca_write64_raw(__be64 val, void __iomem *dest)
static inline void mthca_write64(u32 hi, u32 lo, void __iomem *dest,
static inline void mthca_write64_raw(__be64 val, void __iomem *dest)
static inline void mthca_write64(u32 hi, u32 lo, void __iomem *dest,
void __iomem **map)
u64 __iomem *mtts;
struct mthca_mpt_entry __iomem *mpt;
u64 __iomem *mtts;
void __iomem *reset = ioremap(pci_resource_start(mdev->pdev, 0) +
void __iomem *hw_rxq_prod_addr;
void __iomem *doorbell_addr;
void __iomem *db_addr;
void __iomem *db_addr; /* db address for cons update*/
void __iomem *db; /* Doorbell address */
void __iomem *iwarp_db2; /* Doorbell address */