lib/libnetbsd/sys/cdefs.h

97

((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))

sys/arm64/broadcom/genet/if_genet.c

1007

mdf_ctrl = (__BIT(GENET_MAX_MDF_FILTER) - 1) &~

sys/arm64/broadcom/genet/if_genet.c

1008

(__BIT(GENET_MAX_MDF_FILTER - n) - 1);

sys/arm64/broadcom/genet/if_genet.c

757

WR4(sc, GENET_TX_DMA_RING_CFG, __BIT(qid)); /* enable */

sys/arm64/broadcom/genet/if_genet.c

803

WR4(sc, GENET_RX_DMA_RING_CFG, __BIT(qid)); /* enable */

sys/arm64/broadcom/genet/if_genetreg.h

100

#define GENET_UMAC_MIB_RESET_RX __BIT(0)

sys/arm64/broadcom/genet/if_genetreg.h

102

#define GENET_MDIO_START_BUSY __BIT(29)

sys/arm64/broadcom/genet/if_genetreg.h

103

#define GENET_MDIO_READ_FAILED __BIT(28)

sys/arm64/broadcom/genet/if_genetreg.h

104

#define GENET_MDIO_READ __BIT(27)

sys/arm64/broadcom/genet/if_genetreg.h

105

#define GENET_MDIO_WRITE __BIT(26)

sys/arm64/broadcom/genet/if_genetreg.h

172

#define GENET_RX_DESC_STATUS_OWN __BIT(15) /* ??? */

sys/arm64/broadcom/genet/if_genetreg.h

173

#define GENET_RX_DESC_STATUS_CKSUM_OK __BIT(15)

sys/arm64/broadcom/genet/if_genetreg.h

174

#define GENET_RX_DESC_STATUS_EOP __BIT(14)

sys/arm64/broadcom/genet/if_genetreg.h

175

#define GENET_RX_DESC_STATUS_SOP __BIT(13)

sys/arm64/broadcom/genet/if_genetreg.h

176

#define GENET_RX_DESC_STATUS_RX_ERROR __BIT(2)

sys/arm64/broadcom/genet/if_genetreg.h

182

#define GENET_TX_DESC_STATUS_OWN __BIT(15)

sys/arm64/broadcom/genet/if_genetreg.h

183

#define GENET_TX_DESC_STATUS_EOP __BIT(14)

sys/arm64/broadcom/genet/if_genetreg.h

184

#define GENET_TX_DESC_STATUS_SOP __BIT(13)

sys/arm64/broadcom/genet/if_genetreg.h

186

#define GENET_TX_DESC_STATUS_CRC __BIT(6)

sys/arm64/broadcom/genet/if_genetreg.h

187

#define GENET_TX_DESC_STATUS_CKSUM __BIT(4)

sys/arm64/broadcom/genet/if_genetreg.h

205

#define TXCSUM_LEN_VALID __BIT(31)

sys/arm64/broadcom/genet/if_genetreg.h

207

#define TXCSUM_UDP __BIT(15)

sys/arm64/broadcom/genet/if_genetreg.h

211

#define GENET_RX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)

sys/arm64/broadcom/genet/if_genetreg.h

212

#define GENET_RX_DMA_CTRL_EN __BIT(0)

sys/arm64/broadcom/genet/if_genetreg.h

217

#define GENET_TX_DMA_CTRL_RBUF_EN(qid) __BIT((qid) + 1)

sys/arm64/broadcom/genet/if_genetreg.h

218

#define GENET_TX_DMA_CTRL_EN __BIT(0)

sys/arm64/broadcom/genet/if_genetreg.h

50

#define GENET_SYS_RBUF_FLUSH_RESET __BIT(1)

sys/arm64/broadcom/genet/if_genetreg.h

53

#define GENET_EXT_RGMII_OOB_ID_MODE_DISABLE __BIT(16)

sys/arm64/broadcom/genet/if_genetreg.h

54

#define GENET_EXT_RGMII_OOB_RGMII_MODE_EN __BIT(6)

sys/arm64/broadcom/genet/if_genetreg.h

55

#define GENET_EXT_RGMII_OOB_OOB_DISABLE __BIT(5)

sys/arm64/broadcom/genet/if_genetreg.h

56

#define GENET_EXT_RGMII_OOB_RGMII_LINK __BIT(4)

sys/arm64/broadcom/genet/if_genetreg.h

62

#define GENET_IRQ_MDIO_ERROR __BIT(24)

sys/arm64/broadcom/genet/if_genetreg.h

63

#define GENET_IRQ_MDIO_DONE __BIT(23)

sys/arm64/broadcom/genet/if_genetreg.h

64

#define GENET_IRQ_TXDMA_DONE __BIT(16)

sys/arm64/broadcom/genet/if_genetreg.h

65

#define GENET_IRQ_RXDMA_DONE __BIT(13)

sys/arm64/broadcom/genet/if_genetreg.h

67

#define GENET_RBUF_BAD_DIS __BIT(2)

sys/arm64/broadcom/genet/if_genetreg.h

68

#define GENET_RBUF_ALIGN_2B __BIT(1)

sys/arm64/broadcom/genet/if_genetreg.h

69

#define GENET_RBUF_64B_EN __BIT(0)

sys/arm64/broadcom/genet/if_genetreg.h

71

#define GENET_RBUF_CHECK_CTRL_EN __BIT(0)

sys/arm64/broadcom/genet/if_genetreg.h

72

#define GENET_RBUF_CHECK_SKIP_FCS __BIT(4)

sys/arm64/broadcom/genet/if_genetreg.h

76

#define GENET_UMAC_CMD_LCL_LOOP_EN __BIT(15)

sys/arm64/broadcom/genet/if_genetreg.h

77

#define GENET_UMAC_CMD_SW_RESET __BIT(13)

sys/arm64/broadcom/genet/if_genetreg.h

78

#define GENET_UMAC_CMD_PROMISC __BIT(4)

sys/arm64/broadcom/genet/if_genetreg.h

89

#define GENET_UMAC_CMD_CRC_FWD __BIT(6)

sys/arm64/broadcom/genet/if_genetreg.h

91

#define GENET_UMAC_CMD_RXEN __BIT(1)

sys/arm64/broadcom/genet/if_genetreg.h

92

#define GENET_UMAC_CMD_TXEN __BIT(0)

sys/arm64/broadcom/genet/if_genetreg.h

98

#define GENET_UMAC_MIB_RESET_TX __BIT(2)

sys/arm64/broadcom/genet/if_genetreg.h

99

#define GENET_UMAC_MIB_RESET_RUNT __BIT(1)

sys/dev/bwi/bitops.h

73

((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))

sys/dev/bwi/bwirf.h

128

#define BWI_RFR_BBP_ATTEN_CALIB_BIT __BIT(0)

sys/dev/bwi/if_bwireg.h

100

#define BWI_CAP_CLKMODE __BIT(18)

sys/dev/bwi/if_bwireg.h

110

#define BWI_CLOCK_CTRL_SLOW __BIT(11)

sys/dev/bwi/if_bwireg.h

111

#define BWI_CLOCK_CTRL_IGNPLL __BIT(12)

sys/dev/bwi/if_bwireg.h

112

#define BWI_CLOCK_CTRL_NODYN __BIT(13)

sys/dev/bwi/if_bwireg.h

140

#define BWI_BUS_CONFIG_PREFETCH __BIT(2)

sys/dev/bwi/if_bwireg.h

141

#define BWI_BUS_CONFIG_BURST __BIT(3)

sys/dev/bwi/if_bwireg.h

142

#define BWI_BUS_CONFIG_MRM __BIT(5)

sys/dev/bwi/if_bwireg.h

153

#define BWI_MAC_STATUS_ENABLE __BIT(0)

sys/dev/bwi/if_bwireg.h

154

#define BWI_MAC_STATUS_UCODE_START __BIT(1)

sys/dev/bwi/if_bwireg.h

155

#define BWI_MAC_STATUS_UCODE_JUMP0 __BIT(2)

sys/dev/bwi/if_bwireg.h

156

#define BWI_MAC_STATUS_IHREN __BIT(10)

sys/dev/bwi/if_bwireg.h

158

#define BWI_MAC_STATUS_BSWAP __BIT(16)

sys/dev/bwi/if_bwireg.h

159

#define BWI_MAC_STATUS_INFRA __BIT(17)

sys/dev/bwi/if_bwireg.h

160

#define BWI_MAC_STATUS_OPMODE_HOSTAP __BIT(18)

sys/dev/bwi/if_bwireg.h

161

#define BWI_MAC_STATUS_RFLOCK __BIT(19)

sys/dev/bwi/if_bwireg.h

162

#define BWI_MAC_STATUS_PASS_BCN __BIT(20)

sys/dev/bwi/if_bwireg.h

163

#define BWI_MAC_STATUS_PASS_BADPLCP __BIT(21)

sys/dev/bwi/if_bwireg.h

164

#define BWI_MAC_STATUS_PASS_CTL __BIT(22)

sys/dev/bwi/if_bwireg.h

165

#define BWI_MAC_STATUS_PASS_BADFCS __BIT(23)

sys/dev/bwi/if_bwireg.h

166

#define BWI_MAC_STATUS_PROMISC __BIT(24)

sys/dev/bwi/if_bwireg.h

167

#define BWI_MAC_STATUS_HW_PS __BIT(25)

sys/dev/bwi/if_bwireg.h

168

#define BWI_MAC_STATUS_WAKEUP __BIT(26)

sys/dev/bwi/if_bwireg.h

169

#define BWI_MAC_STATUS_PHYLNK __BIT(31)

sys/dev/bwi/if_bwireg.h

236

#define BWI_TXSTATUS0_VALID __BIT(0)

sys/dev/bwi/if_bwireg.h

237

#define BWI_TXSTATUS0_ACKED __BIT(1)

sys/dev/bwi/if_bwireg.h

239

#define BWI_TXSTATUS0_AMPDU __BIT(5)

sys/dev/bwi/if_bwireg.h

240

#define BWI_TXSTATUS0_PENDING __BIT(6)

sys/dev/bwi/if_bwireg.h

241

#define BWI_TXSTATUS0_PM __BIT(7)

sys/dev/bwi/if_bwireg.h

265

#define BWI_TXRX32_CTRL_ENABLE __BIT(0)

sys/dev/bwi/if_bwireg.h

353

#define BWI_PCIM_GPIO_OUT_CLKSRC __BIT(4)

sys/dev/bwi/if_bwireg.h

356

#define BWI_PCIM_GPIO_PWR_ON __BIT(6)

sys/dev/bwi/if_bwireg.h

357

#define BWI_PCIM_GPIO_PLL_PWR_OFF __BIT(7)

sys/dev/bwi/if_bwireg.h

404

#define BWI_CARD_F_BT_COEXIST __BIT(0) /* Bluetooth coexist */

sys/dev/bwi/if_bwireg.h

405

#define BWI_CARD_F_PA_GPIO9 __BIT(1) /* GPIO 9 controls PA */

sys/dev/bwi/if_bwireg.h

406

#define BWI_CARD_F_SW_NRSSI __BIT(3)

sys/dev/bwi/if_bwireg.h

407

#define BWI_CARD_F_NO_SLOWCLK __BIT(5) /* no slow clock */

sys/dev/bwi/if_bwireg.h

408

#define BWI_CARD_F_EXT_LNA __BIT(12) /* external LNA */

sys/dev/bwi/if_bwireg.h

409

#define BWI_CARD_F_ALT_IQ __BIT(15) /* alternate I/Q */

sys/dev/bwi/if_bwireg.h

414

#define BWI_LED_ACT_LOW __BIT(7)

sys/dev/bwi/if_bwireg.h

467

#define BWI_INTR_READY __BIT(0)

sys/dev/bwi/if_bwireg.h

468

#define BWI_INTR_BEACON __BIT(1)

sys/dev/bwi/if_bwireg.h

469

#define BWI_INTR_TBTT __BIT(2)

sys/dev/bwi/if_bwireg.h

470

#define BWI_INTR_EO_ATIM __BIT(5) /* End of ATIM */

sys/dev/bwi/if_bwireg.h

471

#define BWI_INTR_PMQ __BIT(6) /* XXX?? */

sys/dev/bwi/if_bwireg.h

472

#define BWI_INTR_MAC_TXERR __BIT(9)

sys/dev/bwi/if_bwireg.h

473

#define BWI_INTR_PHY_TXERR __BIT(11)

sys/dev/bwi/if_bwireg.h

474

#define BWI_INTR_TIMER1 __BIT(14)

sys/dev/bwi/if_bwireg.h

475

#define BWI_INTR_RX_DONE __BIT(15)

sys/dev/bwi/if_bwireg.h

476

#define BWI_INTR_TX_FIFO __BIT(16) /* XXX?? */

sys/dev/bwi/if_bwireg.h

477

#define BWI_INTR_NOISE __BIT(18)

sys/dev/bwi/if_bwireg.h

478

#define BWI_INTR_RF_DISABLED __BIT(28)

sys/dev/bwi/if_bwireg.h

479

#define BWI_INTR_TX_DONE __BIT(29)

sys/dev/bwi/if_bwireg.h

49

#define BWI_IMSTATE_INBAND_ERR __BIT(17)

sys/dev/bwi/if_bwireg.h

491

#define BWI_TXRX_INTR_ERROR (__BIT(15) | __BIT(14) | __BITS(12, 10))

sys/dev/bwi/if_bwireg.h

492

#define BWI_TXRX_INTR_RX __BIT(16)

sys/dev/bwi/if_bwireg.h

50

#define BWI_IMSTATE_TIMEOUT __BIT(18)

sys/dev/bwi/if_bwireg.h

55

#define BWI_STATE_LO_RESET __BIT(0)

sys/dev/bwi/if_bwireg.h

56

#define BWI_STATE_LO_DISABLE1 __BIT(1)

sys/dev/bwi/if_bwireg.h

57

#define BWI_STATE_LO_DISABLE2 __BIT(2)

sys/dev/bwi/if_bwireg.h

58

#define BWI_STATE_LO_CLOCK __BIT(16)

sys/dev/bwi/if_bwireg.h

59

#define BWI_STATE_LO_GATED_CLOCK __BIT(17)

sys/dev/bwi/if_bwireg.h

60

#define BWI_STATE_LO_FLAG_PHYCLKEN __BIT(0)

sys/dev/bwi/if_bwireg.h

61

#define BWI_STATE_LO_FLAG_PHYRST __BIT(1)

sys/dev/bwi/if_bwireg.h

62

#define BWI_STATE_LO_FLAG_PHYLNK __BIT(11)

sys/dev/bwi/if_bwireg.h

66

#define BWI_STATE_HI_SERROR __BIT(0)

sys/dev/bwi/if_bwireg.h

67

#define BWI_STATE_HI_BUSY __BIT(2)

sys/dev/bwi/if_bwivar.h

134

#define BWI_DESC32_C_EOR __BIT(28)

sys/dev/bwi/if_bwivar.h

135

#define BWI_DESC32_C_INTR __BIT(29)

sys/dev/bwi/if_bwivar.h

136

#define BWI_DESC32_C_FRAME_END __BIT(30)

sys/dev/bwi/if_bwivar.h

137

#define BWI_DESC32_C_FRAME_START __BIT(31)

sys/dev/bwi/if_bwivar.h

161

#define BWI_RXH_F1_BCM2053_RSSI __BIT(14)

sys/dev/bwi/if_bwivar.h

162

#define BWI_RXH_F1_SHPREAMBLE __BIT(7)

sys/dev/bwi/if_bwivar.h

163

#define BWI_RXH_F1_OFDM __BIT(0)

sys/dev/bwi/if_bwivar.h

165

#define BWI_RXH_F2_TYPE2FRAME __BIT(2)

sys/dev/bwi/if_bwivar.h

167

#define BWI_RXH_F3_BCM2050_RSSI __BIT(10)

sys/dev/bwi/if_bwivar.h

199

#define BWI_TXH_PHY_C_OFDM __BIT(0)

sys/dev/bwi/if_bwivar.h

200

#define BWI_TXH_PHY_C_SHPREAMBLE __BIT(4)

sys/dev/bwi/if_bwivar.h

203

#define BWI_TXH_MAC_C_ACK __BIT(0)

sys/dev/bwi/if_bwivar.h

204

#define BWI_TXH_MAC_C_FIRST_FRAG __BIT(3)

sys/dev/bwi/if_bwivar.h

205

#define BWI_TXH_MAC_C_HWSEQ __BIT(4)

sys/dev/bwi/if_bwivar.h

206

#define BWI_TXH_MAC_C_FB_OFDM __BIT(8)

sys/dev/bwi/if_bwivar.h

222

#define BWI_TXS_F_ACKED __BIT(0)

sys/dev/bwi/if_bwivar.h

223

#define BWI_TXS_F_PENDING __BIT(5)

sys/dev/bwi/if_bwivar.h

311

#define BWI_FW_IV_IS_32BIT __BIT(15)

sys/dev/qat_c2xxx/qat_hw15reg.h

407

#define COMN_RESP_CRYPTO_STATUS __BIT(7)

sys/dev/qat_c2xxx/qat_hw15reg.h

408

#define COMN_RESP_PKE_STATUS __BIT(6)

sys/dev/qat_c2xxx/qat_hw15reg.h

409

#define COMN_RESP_CMP_STATUS __BIT(5)

sys/dev/qat_c2xxx/qat_hw15reg.h

410

#define COMN_RESP_XLAT_STATUS __BIT(4)

sys/dev/qat_c2xxx/qat_hw15reg.h

411

#define COMN_RESP_PM_STATUS __BIT(3)

sys/dev/qat_c2xxx/qat_hw15reg.h

412

#define COMN_RESP_INIT_ADMIN_STATUS __BIT(2)

sys/dev/qat_c2xxx/qat_hw15reg.h

536

#define LA_FLAGS_GCM_IV_LEN_FLAG __BIT(9)

sys/dev/qat_c2xxx/qat_hw15reg.h

542

#define LA_FLAGS_DIGEST_IN_BUFFER __BIT(5)

sys/dev/qat_c2xxx/qat_hw15reg.h

543

#define LA_FLAGS_CMP_AUTH_RES __BIT(4)

sys/dev/qat_c2xxx/qat_hw15reg.h

544

#define LA_FLAGS_RET_AUTH_RES __BIT(3)

sys/dev/qat_c2xxx/qat_hw15reg.h

545

#define LA_FLAGS_UPDATE_STATE __BIT(2)

sys/dev/qat_c2xxx/qat_hw15reg.h

75

#define ARCH_IF_FLAGS_VALID_FLAG __BIT(7)

sys/dev/qat_c2xxx/qatreg.h

112

#define FUSECTL_MASK __BIT(31)

sys/dev/qat_c2xxx/qatreg.h

115

#define LEGFUSE_ACCEL_MASK_CIPHER_SLICE __BIT(0)

sys/dev/qat_c2xxx/qatreg.h

116

#define LEGFUSE_ACCEL_MASK_AUTH_SLICE __BIT(1)

sys/dev/qat_c2xxx/qatreg.h

117

#define LEGFUSE_ACCEL_MASK_PKE_SLICE __BIT(2)

sys/dev/qat_c2xxx/qatreg.h

118

#define LEGFUSE_ACCEL_MASK_COMPRESS_SLICE __BIT(3)

sys/dev/qat_c2xxx/qatreg.h

119

#define LEGFUSE_ACCEL_MASK_LZS_SLICE __BIT(4)

sys/dev/qat_c2xxx/qatreg.h

120

#define LEGFUSE_ACCEL_MASK_EIA3_SLICE __BIT(5)

sys/dev/qat_c2xxx/qatreg.h

121

#define LEGFUSE_ACCEL_MASK_SHA3_SLICE __BIT(6)

sys/dev/qat_c2xxx/qatreg.h

1364

#define HW_AUTH_CONFIG_SHA3_PADDING __BIT(16)

sys/dev/qat_c2xxx/qatreg.h

1473

#define CIPHER_CONFIG_CONVERT __BIT(9)

sys/dev/qat_c2xxx/qatreg.h

1474

#define CIPHER_CONFIG_DIR __BIT(8)

sys/dev/qat_c2xxx/qatreg.h

165

#define ETR_RING_CONFIG_LATE_HEAD_POINTER_MODE __BIT(31)

sys/dev/qat_c2xxx/qatreg.h

238

#define ETR_INT_COL_CTL_ENABLE __BIT(31)

sys/dev/qat_c2xxx/qatreg.h

244

#define ETR_AP_DEST_ENABLE __BIT(7)

sys/dev/qat_c2xxx/qatreg.h

293

#define FCU_STATUS_AUTHFWLD __BIT(8)

sys/dev/qat_c2xxx/qatreg.h

294

#define FCU_STATUS_DONE __BIT(9)

sys/dev/qat_c2xxx/qatreg.h

309

#define CAP_GLOBAL_CTL_MISC_TIMESTAMP_EN __BIT(7)

sys/dev/qat_c2xxx/qatreg.h

329

#define USTORE_ADDRESS_ECS __BIT(31)

sys/dev/qat_c2xxx/qatreg.h

353

#define CTX_ENABLES_INUSE_CONTEXTS __BIT(31)

sys/dev/qat_c2xxx/qatreg.h

354

#define CTX_ENABLES_CNTL_STORE_PARITY_ERROR __BIT(29)

sys/dev/qat_c2xxx/qatreg.h

355

#define CTX_ENABLES_CNTL_STORE_PARITY_ENABLE __BIT(28)

sys/dev/qat_c2xxx/qatreg.h

356

#define CTX_ENABLES_BREAKPOINT __BIT(27)

sys/dev/qat_c2xxx/qatreg.h

357

#define CTX_ENABLES_PAR_ERR __BIT(25)

sys/dev/qat_c2xxx/qatreg.h

358

#define CTX_ENABLES_NN_MODE __BIT(20)

sys/dev/qat_c2xxx/qatreg.h

359

#define CTX_ENABLES_NN_RING_EMPTY __BIT(18)

sys/dev/qat_c2xxx/qatreg.h

360

#define CTX_ENABLES_LMADDR_1_GLOBAL __BIT(17)

sys/dev/qat_c2xxx/qatreg.h

361

#define CTX_ENABLES_LMADDR_0_GLOBAL __BIT(16)

sys/dev/qat_c2xxx/qatreg.h

387

#define ACTIVE_CTX_STATUS_ABO __BIT(31)

sys/dev/qat_c2xxx/qatreg.h

457

#define AE_MISC_CONTROL_PARITY_ENABLE __BIT(24)

sys/dev/qat_c2xxx/qatreg.h

458

#define AE_MISC_CONTROL_FORCE_BAD_PARITY __BIT(23)

sys/dev/qat_c2xxx/qatreg.h

459

#define AE_MISC_CONTROL_ONE_CTX_RELOAD __BIT(22)

sys/dev/qat_c2xxx/qatreg.h

461

#define AE_MISC_CONTROL_SHARE_CS __BIT(2)

sys/dev/qat_c2xxx/qatreg.h

481

#define INTSTATSSM_SHANGERR __BIT(13)

sys/dev/qat_c2xxx/qatreg.h

488

#define SLICE_HANG_AUTH0_MASK __BIT(0)

sys/dev/qat_c2xxx/qatreg.h

489

#define SLICE_HANG_AUTH1_MASK __BIT(1)

sys/dev/qat_c2xxx/qatreg.h

490

#define SLICE_HANG_CPHR0_MASK __BIT(4)

sys/dev/qat_c2xxx/qatreg.h

491

#define SLICE_HANG_CPHR1_MASK __BIT(5)

sys/dev/qat_c2xxx/qatreg.h

492

#define SLICE_HANG_CMP0_MASK __BIT(8)

sys/dev/qat_c2xxx/qatreg.h

493

#define SLICE_HANG_CMP1_MASK __BIT(9)

sys/dev/qat_c2xxx/qatreg.h

494

#define SLICE_HANG_XLT0_MASK __BIT(12)

sys/dev/qat_c2xxx/qatreg.h

495

#define SLICE_HANG_XLT1_MASK __BIT(13)

sys/dev/qat_c2xxx/qatreg.h

496

#define SLICE_HANG_MMP0_MASK __BIT(16)

sys/dev/qat_c2xxx/qatreg.h

497

#define SLICE_HANG_MMP1_MASK __BIT(17)

sys/dev/qat_c2xxx/qatreg.h

498

#define SLICE_HANG_MMP2_MASK __BIT(18)

sys/dev/qat_c2xxx/qatreg.h

499

#define SLICE_HANG_MMP3_MASK __BIT(19)

sys/dev/qat_c2xxx/qatreg.h

500

#define SLICE_HANG_MMP4_MASK __BIT(20)

sys/dev/qat_c2xxx/qatreg.h

525

#define EMSK3_CPM0_MASK __BIT(2)

sys/dev/qat_c2xxx/qatreg.h

526

#define EMSK3_CPM1_MASK __BIT(3)

sys/dev/qat_c2xxx/qatreg.h

527

#define EMSK5_CPM2_MASK __BIT(16)

sys/dev/qat_c2xxx/qatreg.h

528

#define EMSK5_CPM3_MASK __BIT(17)

sys/dev/qat_c2xxx/qatreg.h

529

#define EMSK5_CPM4_MASK __BIT(18)

sys/dev/qat_c2xxx/qatreg.h

68

((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1))

sys/dev/qat_c2xxx/qatreg.h

980

#define AE_MODE_RELOAD_CTX_SHARED __BIT(12)

sys/dev/qat_c2xxx/qatreg.h

981

#define AE_MODE_SHARED_USTORE __BIT(11)

sys/dev/qat_c2xxx/qatreg.h

982

#define AE_MODE_LMEM1 __BIT(9)

sys/dev/qat_c2xxx/qatreg.h

983

#define AE_MODE_LMEM0 __BIT(8)

sys/kern/kern_ubsan.c

1126

HandleTypeMismatch(false, &pData->mLocation, pData->mType, __BIT(pData->mLogAlignment), pData->mTypeCheckKind, ulPointer);

sys/kern/kern_ubsan.c

1135

HandleTypeMismatch(true, &pData->mLocation, pData->mType, __BIT(pData->mLogAlignment), pData->mTypeCheckKind, ulPointer);

sys/kern/kern_ubsan.c

1297

zWidth = __BIT(__SHIFTOUT(pType->mTypeInfo, ~NUMBER_SIGNED_BIT));

sys/kern/kern_ubsan.c

133

#define UBSAN_ABORT __BIT(0)

sys/kern/kern_ubsan.c

134

#define UBSAN_STDOUT __BIT(1)

sys/kern/kern_ubsan.c

135

#define UBSAN_STDERR __BIT(2)

sys/kern/kern_ubsan.c

136

#define UBSAN_SYSLOG __BIT(3)

sys/kern/kern_ubsan.c

95

#define ACK_REPORTED __BIT(31)