Symbol: ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX
sys/arm/xilinx/zy7_slcr.c
343
for (div1 = 1; div1 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX; div1++) {
sys/arm/xilinx/zy7_slcr.c
346
if (div0 > 0 && div0 <= ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX &&
sys/arm/xilinx/zy7_slcr.c
352
if (div1 > ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR_MAX)