Symbol: ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT
sys/arm/xilinx/zy7_slcr.c
364
reg |= (div1 << ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT) |
sys/arm/xilinx/zy7_slcr.c
412
ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_SHIFT;