Symbol: ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK
sys/arm/xilinx/zy7_slcr.c
362
reg &= ~(ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK |
sys/arm/xilinx/zy7_slcr.c
411
div1 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR1_MASK) >>