Symbol: ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK
sys/arm/xilinx/zy7_slcr.c
363
ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK);
sys/arm/xilinx/zy7_slcr.c
413
div0 = (reg & ZY7_SLCR_FPGA_CLK_CTRL_DIVISOR0_MASK) >>