sys/arm/broadcom/bcm2835/bcm2835_sdhost.c

1056

WR1(sc, HC_POWER, val2);

sys/arm/nvidia/as3722.c

233

rv = WR1(sc, AS3722_INTERRUPT_MASK1, 0);

sys/arm/nvidia/as3722.c

236

rv = WR1(sc, AS3722_INTERRUPT_MASK2, 0);

sys/arm/nvidia/as3722.c

239

rv = WR1(sc, AS3722_INTERRUPT_MASK3, 0);

sys/arm/nvidia/as3722.c

242

rv = WR1(sc, AS3722_INTERRUPT_MASK4, 0);

sys/arm/nvidia/as3722_gpio.c

197

rv = WR1(sc, AS3722_GPIO0_CONTROL + pin, ctrl);

sys/arm/nvidia/as3722_gpio.c

444

rv = WR1(sc, AS3722_GPIO0_CONTROL + pin, ctrl);

sys/arm64/nvidia/tegra210/max77620_gpio.c

259

rv = WR1(sc, pin->reg, reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

357

rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue);

sys/arm64/nvidia/tegra210/max77620_gpio.c

366

rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde);

sys/arm64/nvidia/tegra210/max77620_gpio.c

375

rv = WR1(sc, MAX77620_REG_AME_GPIO, sc->gpio_reg_ame);

sys/arm64/nvidia/tegra210/max77620_gpio.c

560

rv = WR1(sc, pin->reg, reg);

sys/arm64/nvidia/tegra210/max77620_gpio.c

566

rv = WR1(sc, MAX77620_REG_PUE_GPIO, sc->gpio_reg_pue);

sys/arm64/nvidia/tegra210/max77620_gpio.c

576

rv = WR1(sc, MAX77620_REG_PDE_GPIO, sc->gpio_reg_pde);

sys/dev/hdmi/dwc_hdmi.c

100

WR1(sc, HDMI_PHY_I2CM_OPERATION_ADDR, HDMI_PHY_I2CM_OPERATION_ADDR_WRITE);

sys/dev/hdmi/dwc_hdmi.c

107

WR1(sc, HDMI_IH_MUTE_FC_STAT2, HDMI_IH_MUTE_FC_STAT2_OVERFLOW_MASK);

sys/dev/hdmi/dwc_hdmi.c

108

WR1(sc, HDMI_FC_MASK2,

sys/dev/hdmi/dwc_hdmi.c

144

WR1(sc, HDMI_FC_INVIDCONF, inv_val);

sys/dev/hdmi/dwc_hdmi.c

147

WR1(sc, HDMI_FC_INHACTV1, sc->sc_mode.hdisplay >> 8);

sys/dev/hdmi/dwc_hdmi.c

148

WR1(sc, HDMI_FC_INHACTV0, sc->sc_mode.hdisplay);

sys/dev/hdmi/dwc_hdmi.c

151

WR1(sc, HDMI_FC_INVACTV1, sc->sc_mode.vdisplay >> 8);

sys/dev/hdmi/dwc_hdmi.c

152

WR1(sc, HDMI_FC_INVACTV0, sc->sc_mode.vdisplay);

sys/dev/hdmi/dwc_hdmi.c

156

WR1(sc, HDMI_FC_INHBLANK1, hblank >> 8);

sys/dev/hdmi/dwc_hdmi.c

157

WR1(sc, HDMI_FC_INHBLANK0, hblank);

sys/dev/hdmi/dwc_hdmi.c

161

WR1(sc, HDMI_FC_INVBLANK, vblank);

sys/dev/hdmi/dwc_hdmi.c

165

WR1(sc, HDMI_FC_HSYNCINDELAY1, hfp >> 8);

sys/dev/hdmi/dwc_hdmi.c

166

WR1(sc, HDMI_FC_HSYNCINDELAY0, hfp);

sys/dev/hdmi/dwc_hdmi.c

170

WR1(sc, HDMI_FC_VSYNCINDELAY, vfp);

sys/dev/hdmi/dwc_hdmi.c

174

WR1(sc, HDMI_FC_HSYNCINWIDTH1, hsync_len >> 8);

sys/dev/hdmi/dwc_hdmi.c

175

WR1(sc, HDMI_FC_HSYNCINWIDTH0, hsync_len);

sys/dev/hdmi/dwc_hdmi.c

178

WR1(sc, HDMI_FC_VSYNCINWIDTH, (sc->sc_mode.vsync_end - sc->sc_mode.vsync_start));

sys/dev/hdmi/dwc_hdmi.c

189

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

200

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

211

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

222

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

233

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

244

WR1(sc, HDMI_PHY_CONF0, reg);

sys/dev/hdmi/dwc_hdmi.c

256

WR1(sc, HDMI_PHY_TST0, val);

sys/dev/hdmi/dwc_hdmi.c

266

WR1(sc, HDMI_MC_SWRSTZ, (uint8_t)~HDMI_MC_SWRSTZ_TMDSSWRST_REQ);

sys/dev/hdmi/dwc_hdmi.c

271

WR1(sc, HDMI_FC_INVIDCONF, val);

sys/dev/hdmi/dwc_hdmi.c

280

WR1(sc, HDMI_MC_FLOWCTRL, HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS);

sys/dev/hdmi/dwc_hdmi.c

289

WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_DEASSERT);

sys/dev/hdmi/dwc_hdmi.c

290

WR1(sc, HDMI_MC_PHYRSTZ, HDMI_MC_PHYRSTZ_ASSERT);

sys/dev/hdmi/dwc_hdmi.c

292

WR1(sc, HDMI_MC_HEACPHY_RST, HDMI_MC_HEACPHY_RST_ASSERT);

sys/dev/hdmi/dwc_hdmi.c

295

WR1(sc, HDMI_PHY_I2CM_SLAVE_ADDR, HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2);

sys/dev/hdmi/dwc_hdmi.c

411

WR1(sc, HDMI_FC_CTRLDUR, 12);

sys/dev/hdmi/dwc_hdmi.c

412

WR1(sc, HDMI_FC_EXCTRLDUR, 32);

sys/dev/hdmi/dwc_hdmi.c

413

WR1(sc, HDMI_FC_EXCTRLSPAC, 1);

sys/dev/hdmi/dwc_hdmi.c

419

WR1(sc, HDMI_FC_CH0PREAM, 0x0B);

sys/dev/hdmi/dwc_hdmi.c

420

WR1(sc, HDMI_FC_CH1PREAM, 0x16);

sys/dev/hdmi/dwc_hdmi.c

421

WR1(sc, HDMI_FC_CH2PREAM, 0x21);

sys/dev/hdmi/dwc_hdmi.c

429

WR1(sc, HDMI_MC_CLKDIS, clkdis);

sys/dev/hdmi/dwc_hdmi.c

432

WR1(sc, HDMI_MC_CLKDIS, clkdis);

sys/dev/hdmi/dwc_hdmi.c

463

WR1(sc, HDMI_AUD_N1, (n >> 0) & 0xff);

sys/dev/hdmi/dwc_hdmi.c

464

WR1(sc, HDMI_AUD_N2, (n >> 8) & 0xff);

sys/dev/hdmi/dwc_hdmi.c

465

WR1(sc, HDMI_AUD_N3, (n >> 16) & 0xff);

sys/dev/hdmi/dwc_hdmi.c

469

WR1(sc, HDMI_AUD_CTS3, val);

sys/dev/hdmi/dwc_hdmi.c

476

WR1(sc, HDMI_AUD_CONF0, val);

sys/dev/hdmi/dwc_hdmi.c

483

WR1(sc, HDMI_AUD_CONF1, val);

sys/dev/hdmi/dwc_hdmi.c

485

WR1(sc, HDMI_AUD_INPUTCLKFS, HDMI_AUD_INPUTCLKFS_64);

sys/dev/hdmi/dwc_hdmi.c

487

WR1(sc, HDMI_FC_AUDICONF0, 1 << 4); /* CC=1 */

sys/dev/hdmi/dwc_hdmi.c

488

WR1(sc, HDMI_FC_AUDICONF1, 0);

sys/dev/hdmi/dwc_hdmi.c

489

WR1(sc, HDMI_FC_AUDICONF2, 0); /* CA=0 */

sys/dev/hdmi/dwc_hdmi.c

490

WR1(sc, HDMI_FC_AUDICONF3, 0);

sys/dev/hdmi/dwc_hdmi.c

491

WR1(sc, HDMI_FC_AUDSV, 0xee); /* channels valid */

sys/dev/hdmi/dwc_hdmi.c

496

WR1(sc, HDMI_MC_CLKDIS, val);

sys/dev/hdmi/dwc_hdmi.c

513

WR1(sc, HDMI_VP_PR_CD, val);

sys/dev/hdmi/dwc_hdmi.c

518

WR1(sc, HDMI_VP_STUFF, val);

sys/dev/hdmi/dwc_hdmi.c

525

WR1(sc, HDMI_VP_CONF, val);

sys/dev/hdmi/dwc_hdmi.c

530

WR1(sc, HDMI_VP_STUFF, val);

sys/dev/hdmi/dwc_hdmi.c

532

WR1(sc, HDMI_VP_REMAP, remap_size);

sys/dev/hdmi/dwc_hdmi.c

542

WR1(sc, HDMI_VP_CONF, val);

sys/dev/hdmi/dwc_hdmi.c

551

WR1(sc, HDMI_VP_CONF, val);

sys/dev/hdmi/dwc_hdmi.c

560

WR1(sc, HDMI_VP_CONF, val);

sys/dev/hdmi/dwc_hdmi.c

570

WR1(sc, HDMI_VP_STUFF, val);

sys/dev/hdmi/dwc_hdmi.c

575

WR1(sc, HDMI_VP_CONF, val);

sys/dev/hdmi/dwc_hdmi.c

588

WR1(sc, HDMI_TX_INVID0, val);

sys/dev/hdmi/dwc_hdmi.c

594

WR1(sc, HDMI_TX_INSTUFFING, val);

sys/dev/hdmi/dwc_hdmi.c

595

WR1(sc, HDMI_TX_GYDATA0, 0x0);

sys/dev/hdmi/dwc_hdmi.c

596

WR1(sc, HDMI_TX_GYDATA1, 0x0);

sys/dev/hdmi/dwc_hdmi.c

597

WR1(sc, HDMI_TX_RCRDATA0, 0x0);

sys/dev/hdmi/dwc_hdmi.c

598

WR1(sc, HDMI_TX_RCRDATA1, 0x0);

sys/dev/hdmi/dwc_hdmi.c

599

WR1(sc, HDMI_TX_BCBDATA0, 0x0);

sys/dev/hdmi/dwc_hdmi.c

600

WR1(sc, HDMI_TX_BCBDATA1, 0x0);

sys/dev/hdmi/dwc_hdmi.c

614

WR1(sc, HDMI_A_HDCPCFG0, val);

sys/dev/hdmi/dwc_hdmi.c

620

WR1(sc, HDMI_A_VIDPOLCFG, val);

sys/dev/hdmi/dwc_hdmi.c

626

WR1(sc, HDMI_A_HDCPCFG1, val);

sys/dev/hdmi/dwc_hdmi.c

741

WR1(sc, HDMI_PHY_POL0, HDMI_PHY_POL0_HPD);

sys/dev/hdmi/dwc_hdmi.c

742

WR1(sc, HDMI_IH_PHY_STAT0, HDMI_IH_PHY_STAT0_HPD);

sys/dev/hdmi/dwc_hdmi.c

95

WR1(sc, HDMI_IH_I2CMPHY_STAT0,

sys/dev/hdmi/dwc_hdmi.c

97

WR1(sc, HDMI_PHY_I2CM_ADDRESS_ADDR, addr);

sys/dev/hdmi/dwc_hdmi.c

98

WR1(sc, HDMI_PHY_I2CM_DATAO_1_ADDR, ((data >> 8) & 0xff));

sys/dev/hdmi/dwc_hdmi.c

99

WR1(sc, HDMI_PHY_I2CM_DATAO_0_ADDR, ((data >> 0) & 0xff));

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

246

WR1(sc, CDNC_I2C_TIME_OUT, CDNC_I2C_TIME_OUT_MAX);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

353

WR1(sc, CDNC_I2C_TRANS_SIZE, nbytes);

sys/dev/sdhci/sdhci.c

1275

WR1(slot, SDHCI_SOFTWARE_RESET, mask);

sys/dev/sdhci/sdhci.c

1397

WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);

sys/dev/sdhci/sdhci.c

1958

WR1(slot, SDHCI_TIMEOUT_CONTROL, div);

sys/dev/sdhci/sdhci.c

2203

WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl |= SDHCI_CTRL_LED);

sys/dev/sdhci/sdhci.c

2215

WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl &= ~SDHCI_CTRL_LED);

sys/dev/sdhci/sdhci.c

2870

WR1(slot, SDHCI_HOST_CONTROL, slot->hostctrl);

sys/dev/sdhci/sdhci.c

521

WR1(slot, SDHCI_POWER_CONTROL, pwr);

sys/dev/sdhci/sdhci.c

539

WR1(slot, SDHCI_POWER_CONTROL, pwr);

sys/dev/sdhci/sdhci.c

547

WR1(slot, SDHCI_POWER_CONTROL, pwr);

sys/dev/sdhci/sdhci.c

556

WR1(slot, SDHCI_POWER_CONTROL, pwr | 0x10);

sys/dev/sdhci/sdhci.c

558

WR1(slot, SDHCI_POWER_CONTROL, pwr);