XGMAC_SET_BITS
XGMAC_SET_BITS(dma_status, DMA_CH_SR, TI, 1);
XGMAC_SET_BITS(dma_status, DMA_CH_SR, RI, 1);
XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, TI, 0);
XGMAC_SET_BITS(dma_ch_isr, DMA_CH_SR, RI, 0);
XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, IP2TE, 1);
XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, TCP4TE, 1);
XGMAC_SET_BITS(pdata->rss_options, MAC_RSSCR, UDP4TE, 1);
XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, qid);
XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH,
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, RA, reg);
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, PA, port);
XGMAC_SET_BITS(mdio_sca, MAC_MDIOSCAR, DA, da);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, DATA, val);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 1);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, CMD, 3);
XGMAC_SET_BITS(mdio_sccd, MAC_MDIOSCCDR, BUSY, 1);
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES, CONTEXT, 0);
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->attributes, RX_PACKET_ATTRIBUTES,
XGMAC_SET_BITS(packet->errors, RX_PACKET_ERRORS,
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TXSE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TBUE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RSE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, TIE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RIE, 0);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 0);
XGMAC_SET_BITS(sbmr, DMA_SBMR, EAME, 1);
XGMAC_SET_BITS(sbmr, DMA_SBMR, UNDEF, 1);
XGMAC_SET_BITS(sbmr, DMA_SBMR, BLEN, pdata->blen >> 2);
XGMAC_SET_BITS(sbmr, DMA_SBMR, AAL, pdata->aal);
XGMAC_SET_BITS(sbmr, DMA_SBMR, RD_OSR_LMT, pdata->rd_osr_limit - 1);
XGMAC_SET_BITS(sbmr, DMA_SBMR, WR_OSR_LMT, pdata->wr_osr_limit - 1);
XGMAC_SET_BITS(pdata->rss_table[i], MAC_RSSDR, DMCH, table[i]);
XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 0);
XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, TFE, 1);
XGMAC_SET_BITS(reg_val, MAC_Q0TFCR, PT, 0xffff);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE20, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE20, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, NIE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, AIE, 1);
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, FBEE, 1);
XGMAC_SET_BITS(channel->curr_ier,
XGMAC_SET_BITS(channel->curr_ier, DMA_CH_IER, RBUE, 1);
XGMAC_SET_BITS(channel->curr_ier,
XGMAC_SET_BITS(mac_ier, MAC_IER, TSIE, 1);
XGMAC_SET_BITS(mac_addr_hi, MAC_MACA1HR, AE, 1);