Symbol: WRITE_REG32
sys/dev/qlxgb/qla_hw.h
795
WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->rds_rsp[i].producer_reg +\
sys/dev/qlxgb/qla_hw.h
799
WRITE_REG32(ha, (ha->hw.tx_prod_reg + 0x1b2000), val)
sys/dev/qlxgb/qla_hw.h
802
WRITE_REG32(ha, ((ha->hw.rx_cntxt_rsp)->sds_rsp[i].consumer_reg +\
sys/dev/qlxgb/qla_hw.h
807
WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F0, 0xFFFFFFFF);\
sys/dev/qlxgb/qla_hw.h
809
WRITE_REG32(ha, Q8_INT_TARGET_STATUS_F1, 0xFFFFFFFF);\
sys/dev/qlxgb/qla_hw.h
816
WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x1);\
sys/dev/qlxgb/qla_hw.h
823
WRITE_REG32(ha, (rsp_sds->intr_mask_reg + 0x1b2000), 0x0);\
sys/dev/qlxgbe/ql_hw.c
1434
WRITE_REG32(ha, (Q8_HOST_MBOX0 + (i << 2)), *h_mbox);
sys/dev/qlxgbe/ql_hw.c
1438
WRITE_REG32(ha, Q8_HOST_MBOX_CNTRL, 0x1);
sys/dev/qlxgbe/ql_hw.c
1480
WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
sys/dev/qlxgbe/ql_hw.c
1481
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
sys/dev/qlxgbe/ql_hw.c
2863
WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
sys/dev/qlxgbe/ql_hw.c
2864
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
sys/dev/qlxgbe/ql_hw.h
1719
WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
sys/dev/qlxgbe/ql_inline.h
64
WRITE_REG32(ha, id_reg, id_val);
sys/dev/qlxgbe/ql_ioctl.c
118
WRITE_REG32(ha, u.rv->reg, u.rv->val);
sys/dev/qlxgbe/ql_isr.c
765
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
sys/dev/qlxgbe/ql_isr.c
881
WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
sys/dev/qlxgbe/ql_isr.c
882
WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
sys/dev/qlxgbe/ql_misc.c
1307
WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
sys/dev/qlxgbe/ql_misc.c
1315
WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
sys/dev/qlxgbe/ql_misc.c
1387
WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0);
sys/dev/qlxgbe/ql_misc.c
1395
WRITE_REG32(ha, Q8_FW_IMAGE_VALID, 0x12345678);
sys/dev/qlxgbe/ql_misc.c
70
WRITE_REG32(ha, wnd_reg, addr);
sys/dev/qlxgbe/ql_misc.c
87
WRITE_REG32(ha, Q8_WILD_CARD, *val);
sys/dev/qlxge/qls_dump.c
1218
WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
sys/dev/qlxge/qls_dump.c
1231
WRITE_REG32(ha, Q81_CTL_XG_PROBE_MUX_ADDR,\
sys/dev/qlxge/qls_dump.c
1420
WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, val);
sys/dev/qlxge/qls_dump.c
1526
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX,\
sys/dev/qlxge/qls_dump.c
1556
WRITE_REG32(ha, Q81_CTL_NIC_ENH_TX_SCHD, \
sys/dev/qlxge/qls_dump.c
1562
WRITE_REG32(ha, Q81_CTL_CNA_ENH_TX_SCHD, \
sys/dev/qlxge/qls_dump.c
1925
WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, 0x80008000);
sys/dev/qlxge/qls_dump.c
404
WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg | Q81_CTL_PROC_ADDR_READ);
sys/dev/qlxge/qls_dump.c
428
WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
sys/dev/qlxge/qls_dump.c
430
WRITE_REG32(ha, Q81_CTL_PROC_ADDR, reg);
sys/dev/qlxge/qls_dump.c
609
WRITE_REG32(ha, Q81_CTL_XG_SERDES_ADDR, \
sys/dev/qlxge/qls_dump.c
813
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
sys/dev/qlxge/qls_dump.c
825
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, \
sys/dev/qlxge/qls_dump.c
849
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (0x037f0300 + i));
sys/dev/qlxge/qls_dump.c
865
WRITE_REG32(ha, Q81_CTL_XGMAC_ADDR, (reg | Q81_XGMAC_ADDR_R));
sys/dev/qlxge/qls_hw.c
1023
WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
sys/dev/qlxge/qls_hw.c
1026
WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
sys/dev/qlxge/qls_hw.c
1033
WRITE_REG32(ha, Q81_CTL_CONFIG, value);
sys/dev/qlxge/qls_hw.c
1102
WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
sys/dev/qlxge/qls_hw.c
1105
WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
sys/dev/qlxge/qls_hw.c
1112
WRITE_REG32(ha, Q81_CTL_CONFIG, value);
sys/dev/qlxge/qls_hw.c
1172
WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_LO, value);
sys/dev/qlxge/qls_hw.c
1175
WRITE_REG32(ha, Q81_CTL_ICB_ACCESS_ADDR_HI, value);
sys/dev/qlxge/qls_hw.c
1182
WRITE_REG32(ha, Q81_CTL_CONFIG, value);
sys/dev/qlxge/qls_hw.c
1791
WRITE_REG32(ha, Q81_CTL_FLASH_ADDR, (addr | Q81_CTL_FLASH_ADDR_R));
sys/dev/qlxge/qls_hw.c
1887
WRITE_REG32(ha, Q81_CTL_SEMAPHORE, (mask|value));
sys/dev/qlxge/qls_hw.c
1904
WRITE_REG32(ha, Q81_CTL_SEMAPHORE, mask);
sys/dev/qlxge/qls_hw.c
1946
WRITE_REG32(ha, Q81_CTL_PROC_ADDR, value);
sys/dev/qlxge/qls_hw.c
1971
WRITE_REG32(ha, Q81_CTL_PROC_DATA, data);
sys/dev/qlxge/qls_hw.c
1975
WRITE_REG32(ha, Q81_CTL_PROC_ADDR, value);
sys/dev/qlxge/qls_hw.c
1994
WRITE_REG32(ha, Q81_CTL_RESET, data);
sys/dev/qlxge/qls_hw.c
2170
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_SET_HTR_INTR);
sys/dev/qlxge/qls_hw.c
2208
WRITE_REG32(ha,\
sys/dev/qlxge/qls_hw.c
2228
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
sys/dev/qlxge/qls_hw.c
2388
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
sys/dev/qlxge/qls_hw.c
2395
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS,\
sys/dev/qlxge/qls_hw.c
263
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
sys/dev/qlxge/qls_hw.c
264
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
sys/dev/qlxge/qls_hw.c
273
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
sys/dev/qlxge/qls_hw.c
274
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
sys/dev/qlxge/qls_hw.c
283
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
sys/dev/qlxge/qls_hw.c
289
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, value);
sys/dev/qlxge/qls_hw.c
328
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
sys/dev/qlxge/qls_hw.c
329
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_lower);
sys/dev/qlxge/qls_hw.c
339
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_INDEX, value);
sys/dev/qlxge/qls_hw.c
340
WRITE_REG32(ha, Q81_CTL_MAC_PROTO_ADDR_DATA, mac_upper);
sys/dev/qlxge/qls_hw.c
383
WRITE_REG32(ha, Q81_CTL_ROUTING_INDEX, index);
sys/dev/qlxge/qls_hw.c
384
WRITE_REG32(ha, Q81_CTL_ROUTING_DATA, data);
sys/dev/qlxge/qls_hw.c
799
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
sys/dev/qlxge/qls_hw.c
802
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
sys/dev/qlxge/qls_hw.c
835
WRITE_REG32(ha, Q81_CTL_SYSTEM, value);
sys/dev/qlxge/qls_hw.c
839
WRITE_REG32(ha, Q81_CTL_NIC_RCV_CONFIG, value);
sys/dev/qlxge/qls_hw.c
854
WRITE_REG32(ha, Q81_CTL_FUNC_SPECIFIC, value);
sys/dev/qlxge/qls_hw.c
860
WRITE_REG32(ha, Q81_CTL_INTR_MASK, value);
sys/dev/qlxge/qls_hw.c
907
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
sys/dev/qlxge/qls_hw.c
913
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, value);
sys/dev/qlxge/qls_hw.h
910
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRE_MASK_VALUE | idx))
sys/dev/qlxge/qls_hw.h
917
WRITE_REG32(ha, Q81_CTL_INTR_ENABLE, (Q81_CTL_INTRD_MASK_VALUE | idx))
sys/dev/qlxge/qls_isr.c
355
WRITE_REG32(ha, Q81_CTL_HOST_CMD_STATUS, Q81_CTL_HCS_CMD_CLR_RTH_INTR);