WRITE_OFFSET32
WRITE_OFFSET32(ha, Q8_NX_CDRP_SIGNATURE, signature);
WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG1, (cdrp->cmd_arg1));
WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG2, (cdrp->cmd_arg2));
WRITE_OFFSET32(ha, Q8_NX_CDRP_ARG3, (cdrp->cmd_arg3));
WRITE_OFFSET32(ha, Q8_NX_CDRP_CMD_RSP, cdrp->cmd);
WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0xFFFFFFFF);
WRITE_OFFSET32(ha, id_reg, id_val);
WRITE_OFFSET32(ha, rv->reg, rv->val);
WRITE_OFFSET32(ha, Q8_CRB_WINDOW_2M, offset);
WRITE_OFFSET32(ha, ((addr & 0xFFFF) | 0x1E0000), *val);
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_ADDR_LO, (uint32_t)addr);
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_ADDR_HI, (uint32_t)(addr >> 32));
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_LO, val->data_lo);
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_HI, val->data_hi);
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_ULO, val->data_ulo);
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_WRDATA_UHI, val->data_uhi);
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_CTRL, 0x07); /* Write */
WRITE_OFFSET32(ha, Q8_MIU_TEST_AGT_CTRL, 0x03); /* Read */
WRITE_OFFSET32(ha, Q8_ROM_LOCKID, 0xa5a5a5a5);
WRITE_OFFSET32(ha, Q8_ROM_LOCKID, 0xa5a5a5a5);
WRITE_OFFSET32(ha, Q8_PEG_D_RESET1, 0x001E);
WRITE_OFFSET32(ha, Q8_PEG_D_RESET2, 0x0008);
WRITE_OFFSET32(ha, Q8_PEG_I_RESET, 0x0008);
WRITE_OFFSET32(ha, Q8_PEG_0_CLR1, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_0_CLR2, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_1_CLR1, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_1_CLR2, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_2_CLR1, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_2_CLR2, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_3_CLR1, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_3_CLR2, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_4_CLR1, 0x0000);
WRITE_OFFSET32(ha, Q8_PEG_4_CLR2, 0x0000);
WRITE_OFFSET32(ha, Q8_CMDPEG_STATE, 0x00000000);
WRITE_OFFSET32(ha, Q8_PEG_0_RESET, 0x00001020);
WRITE_OFFSET32(ha, Q8_ASIC_RESET, 0x0080001E);