sys/arm/broadcom/bcm2835/bcm2835_sdhost.c

1096

WR2(sc, HC_BLOCKSIZE, val);

sys/arm/broadcom/bcm2835/bcm2835_sdhost.c

1103

WR2(sc, HC_BLOCKCOUNT, val);

sys/arm/freescale/imx/imx_wdog.c

114

WR2(sc, WDOG_CR_REG, reg | WDOG_CR_WDE);

sys/arm/freescale/imx/imx_wdog.c

117

WR2(sc, WDOG_SR_REG, WDOG_SR_STEP1);

sys/arm/freescale/imx/imx_wdog.c

118

WR2(sc, WDOG_SR_REG, WDOG_SR_STEP2);

sys/arm/freescale/imx/imx_wdog.c

123

WR2(sc, WDOG_MCR_REG, reg & ~WDOG_MCR_PDE);

sys/arm/freescale/imx/imx_wdog.c

206

WR2(sc, WDOG_CR_REG, WDOG_CR_WDT | RD2(sc, WDOG_CR_REG));

sys/arm/freescale/imx/imx_wdog.c

210

WR2(sc, WDOG_ICR_REG, WDOG_ICR_WIE); /* Enable, count is 0. */

sys/dev/ffec/if_ffec.c

294

WR2(sc, FEC_MIIGSK_ENR, 0);

sys/dev/ffec/if_ffec.c

298

WR2(sc, FEC_MIIGSK_CFGR, ifmode);

sys/dev/ffec/if_ffec.c

300

WR2(sc, FEC_MIIGSK_ENR, FEC_MIIGSK_ENR_EN);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

224

WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

238

WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

242

WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

243

WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

262

WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

313

WR2(sc, CDNC_I2C_ISR, status);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

348

WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

359

WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

365

WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

370

WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DONE |

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

373

WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DATA |

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

379

WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_XFER_DATA |

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

422

WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow | CDNC_I2C_CR_CLR_FIFO);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

431

WR2(sc, CDNC_I2C_DATA, msg->buf[idx++]);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

437

WR2(sc, CDNC_I2C_CR, sc->cfg_reg_shadow);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

443

WR2(sc, CDNC_I2C_ADDR, msg->slave >> 1);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

447

WR2(sc, CDNC_I2C_IER, CDNC_I2C_ISR_XFER_DONE |

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

454

WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_XFER_DONE |

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

639

WR2(sc, CDNC_I2C_CR, CDNC_I2C_CR_CLR_FIFO);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

642

WR2(sc, CDNC_I2C_ISR, CDNC_I2C_ISR_ALL);

sys/dev/iicbus/controller/cadence/cdnc_i2c.c

643

WR2(sc, CDNC_I2C_IDR, CDNC_I2C_ISR_ALL);

sys/dev/sdhci/sdhci.c

1360

WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);

sys/dev/sdhci/sdhci.c

1428

WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);

sys/dev/sdhci/sdhci.c

1443

WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2);

sys/dev/sdhci/sdhci.c

1601

WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 | SDHCI_CTRL2_EXEC_TUNING);

sys/dev/sdhci/sdhci.c

1644

WR2(slot, SDHCI_HOST_CONTROL2, hostctrl2 & ~(SDHCI_CTRL2_EXEC_TUNING |

sys/dev/sdhci/sdhci.c

1747

WR2(slot, SDHCI_TRANSFER_MODE, mode);

sys/dev/sdhci/sdhci.c

1862

WR2(slot, SDHCI_COMMAND_FLAGS, (cmd->opcode << 8) | (flags & 0xff));

sys/dev/sdhci/sdhci.c

2014

WR2(slot, SDHCI_BLOCK_SIZE, blksz);

sys/dev/sdhci/sdhci.c

2015

WR2(slot, SDHCI_BLOCK_COUNT, blkcnt);

sys/dev/sdhci/sdhci.c

424

WR2(slot, SDHCI_CLOCK_CONTROL, clk & ~SDHCI_CLOCK_CARD_EN);

sys/dev/sdhci/sdhci.c

447

WR2(slot, BCM577XX_HOST_CONTROL, clk_sel);

sys/dev/sdhci/sdhci.c

486

WR2(slot, SDHCI_CLOCK_CONTROL, clk);

sys/dev/sdhci/sdhci.c

489

WR2(slot, SDHCI_CLOCK_CONTROL, clk);

sys/dev/sdhci/sdhci.c

505

WR2(slot, SDHCI_CLOCK_CONTROL, clk);