sys/arm64/vmm/io/vgic_v3.c

257

VGIC_REGISTER_RAZ_WI(GICD_STATUSR, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

262

VGIC_REGISTER_RAZ_WI(GICD_SETSPI_SR, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

263

VGIC_REGISTER_RAZ_WI(GICD_CLRSPI_SR, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

267

VGIC_REGISTER_RAZ_WI(GICD_ISENABLER(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

271

VGIC_REGISTER_RAZ_WI(GICD_ICENABLER(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

275

VGIC_REGISTER_RAZ_WI(GICD_ISPENDR(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

279

VGIC_REGISTER_RAZ_WI(GICD_ICPENDR(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

283

VGIC_REGISTER_RAZ_WI(GICD_ISACTIVER(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

287

VGIC_REGISTER_RAZ_WI(GICD_ICACTIVER(0), 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

310

VGIC_REGISTER_RAZ_WI(GICD_SGIR, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

351

VGIC_REGISTER_RAZ_WI(GICR_STATUSR, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

352

VGIC_REGISTER_RAZ_WI(GICR_WAKER, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

353

VGIC_REGISTER_RAZ_WI(GICR_SETLPIR, 8, VGIC_64_BIT | VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

354

VGIC_REGISTER_RAZ_WI(GICR_CLRLPIR, 8, VGIC_64_BIT | VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

355

VGIC_REGISTER_RAZ_WI(GICR_PROPBASER, 8, VGIC_64_BIT | VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

356

VGIC_REGISTER_RAZ_WI(GICR_PENDBASER, 8, VGIC_64_BIT | VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

357

VGIC_REGISTER_RAZ_WI(GICR_INVLPIR, 8, VGIC_64_BIT | VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

358

VGIC_REGISTER_RAZ_WI(GICR_INVALLR, 8, VGIC_64_BIT | VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

359

VGIC_REGISTER_RAZ_WI(GICR_SYNCR, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

396

VGIC_REGISTER_RAZ_WI(GICR_IGROUPR0, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

412

VGIC_REGISTER_RAZ_WI(GICR_ICFGR0, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

415

VGIC_REGISTER_RAZ_WI(GICR_IGRPMODR0, 4, VGIC_32_BIT),

sys/arm64/vmm/io/vgic_v3.c

416

VGIC_REGISTER_RAZ_WI(GICR_NSACR, 4, VGIC_32_BIT),