VSC_REG
{ VSC_REG(7, 15, 0xf), 2 },
{ VSC_REG(7, 15, 0x19), 0xd6 },
{ VSC_REG(7, 15, 7), 0xc },
{ VSC_REG(7, 1, 0), 0x220 },
{ VSC_REG(2, 0, 0x2f), 0 },
{ VSC_REG(2, 0, 0xf), 0xa0010291 },
{ VSC_REG(2, 1, 0x2f), 1 },
{ VSC_REG(2, 1, 0xf), 0xa026301 }
{ VSC_REG(1, 10, 0), 0x600b },
{ VSC_REG(1, 10, 1), 0x70600 }, //QUANTA = 96*1024*8/512
{ VSC_REG(1, 10, 2), 0x2710 },
{ VSC_REG(1, 10, 5), 0x65 },
{ VSC_REG(1, 10, 7), 0x23 },
{ VSC_REG(1, 10, 0x23), 0x800007bf },
{ VSC_REG(1, 10, 0x23), 0x000007bf },
{ VSC_REG(1, 10, 0x23), 0x800007bf },
{ VSC_REG(1, 10, 0x24), 4 }
(ret = elmr_write(adap, VSC_REG(2, 0, 0x10 + i),
(ret = elmr_write(adap, VSC_REG(2, 0, 0x40 + i),
(ret = elmr_write(adap, VSC_REG(2, 0, 0x50 + i), 1)) ||
(ret = elmr_write(adap, VSC_REG(2, 1, 0x10 + i),
(ret = elmr_write(adap, VSC_REG(2, 1, 0x40 + i),
(ret = elmr_write(adap, VSC_REG(2, 1, 0x50 + i), 0)))
if ((ret = elmr_write(adap, VSC_REG(1, i, 0), 0xa59c)) ||
(ret = elmr_write(adap, VSC_REG(1, i, 5),
(ret = elmr_write(adap, VSC_REG(1, i, 0xb), 0x96)) ||
(ret = elmr_write(adap, VSC_REG(1, i, 0x15), 0x21)) ||
if ((r = elmr_write(adap, VSC_REG(1, port, 0),
(r = elmr_write(adap, VSC_REG(1, port, 0xb),
(r = elmr_write(adap, VSC_REG(1, port, 0xb),
(r = elmr_write(adap, VSC_REG(1, port, 0),
return elmr_write(adap, VSC_REG(1, port, 1), r);
return elmr_write(adap, VSC_REG(1, port, 2), mtu);
ret = elmr_write(adap, VSC_REG(1, port, 3),
ret = elmr_write(adap, VSC_REG(1, port, 4),
ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1);
ret = elmr_write(adap, VSC_REG(1, port, 0), v);
ret = t3_elmr_blk_read(adap, VSC_REG(1, port, 0), &v, 1);
ret = elmr_write(adap, VSC_REG(1, port, 0), v);