VM_MEMATTR_DEVICE
VM_PROT_READ | VM_PROT_WRITE, VM_MEMATTR_DEVICE);
CTASSERT(VM_MEMATTR_DEVICE == 2);
pmap_kenter(va, size, pa, VM_MEMATTR_DEVICE);
pmap_remap_vm_attr(VM_MEMATTR_DEVICE, VM_MEMATTR_SO);
ma = VM_MEMATTR_DEVICE;
mode = VM_MEMATTR_DEVICE;
if (mode == VM_MEMATTR_DEVICE || p->md_attr & EFI_MD_ATTR_XP)
return (VM_MEMATTR_DEVICE);
return (VM_MEMATTR_DEVICE);
pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
m->md.pv_memattr == VM_MEMATTR_DEVICE)
m->md.pv_memattr == VM_MEMATTR_DEVICE)
m->md.pv_memattr == VM_MEMATTR_DEVICE)
if (mode == VM_MEMATTR_DEVICE) {
if (memattr == VM_MEMATTR_DEVICE)
case VM_MEMATTR_DEVICE:
case ATTR_S1_IDX(VM_MEMATTR_DEVICE):
ATTR_S1_IDX(VM_MEMATTR_DEVICE) | IOMMU_L3_PAGE);
ptr[3] = MAIR_ATTR(MAIR_DEVICE_nGnRnE, VM_MEMATTR_DEVICE) |
#ifdef VM_MEMATTR_DEVICE
_ioremap_attr((addr), (size), VM_MEMATTR_DEVICE)
_ioremap_attr((addr), (size), VM_MEMATTR_DEVICE)
_ioremap_attr((addr), (size), VM_MEMATTR_DEVICE)
{ VM_MEMATTR_DEVICE, "cache-inhibited part" },
{ VM_MEMATTR_DEVICE, "control registers" }
req.memattr = VM_MEMATTR_DEVICE;
req.memattr = VM_MEMATTR_DEVICE;
req.memattr = VM_MEMATTR_DEVICE;
memattr = VM_MEMATTR_DEVICE;
args->memattr = VM_MEMATTR_DEVICE;
VM_PROT_READ | VM_PROT_WRITE, VM_MEMATTR_DEVICE);
return (pmap_mapdev_attr(pa, size, VM_MEMATTR_DEVICE));
KASSERT(ma == VM_MEMATTR_DEVICE,
#define VM_MEMATTR_LAST VM_MEMATTR_DEVICE
pmap_kenter(sva, size, pa, VM_MEMATTR_DEVICE);
case VM_MEMATTR_DEVICE:
memattr_bits[VM_MEMATTR_DEVICE] = PTE_MA_IO;
memattr_bits[VM_MEMATTR_DEVICE] = PTE_THEAD_MA_IO;
#ifdef VM_MEMATTR_DEVICE
MEMATTR_STR(VM_MEMATTR_DEVICE, "DEV")
MEMATTR_STR(VM_MEMATTR_DEVICE, "NP")
pbm.pbm_memattr = VM_MEMATTR_DEVICE;
pbm.pbm_memattr = VM_MEMATTR_DEVICE;