UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV
reg &= ~UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(~0);
reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x19);
reg |= UPHY_PLL_S0_CTL1_PLL0_FREQ_NDIV(0x1e);