Symbol: UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
576
reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
577
reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
799
reg &= ~UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(~0);
sys/arm64/nvidia/tegra210/tegra210_xusbpadctl.c
800
reg |= UPHY_PLL_P0_CTL5_PLL0_DCO_CTRL(0x2a);