Symbol: UL
crypto/libecc/include/libecc/words/types.h
140
#define UINT8_C(c) ((uint8_t)(c ## UL))
crypto/libecc/include/libecc/words/types.h
141
#define UINT16_C(c) ((uint16_t)(c ## UL))
crypto/libecc/include/libecc/words/types.h
142
#define UINT32_C(c) ((uint32_t)(c ## UL))
crypto/openssl/crypto/aes/aes_core.c
58
#define U64(C) C##UL
crypto/openssl/crypto/aes/aes_x86core.c
85
#define U64(C) C##UL
crypto/openssl/crypto/bn/bn_srp.c
22
#define bn_pack4(a1, a2, a3, a4) ((a1##UL << 48) | (a2##UL << 32) | (a3##UL << 16) | a4##UL)
crypto/openssl/crypto/bn/bn_srp.c
27
#define bn_pack4(a1, a2, a3, a4) ((a3##UL << 16) | a4##UL), ((a1##UL << 16) | a2##UL)
crypto/openssl/crypto/sha/sha512.c
69
#define U64(C) C##UL
crypto/openssl/include/crypto/modes.h
20
#define U64(C) C##UL
crypto/openssl/include/internal/numbers.h
72
#define UINT64_C(c) (c##UL)
crypto/openssl/include/internal/numbers.h
81
#define UINT32_C(c) (c##UL)
crypto/openssl/test/bad_dtls_test.c
649
#define NODROP(x) { x##UL, 0 }
crypto/openssl/test/bad_dtls_test.c
650
#define DROP(x) { x##UL, 1 }
sbin/ipf/ipftest/md5.c
208
FF ( a, b, c, d, in[ 0], S11, UL(3614090360)); /* 1 */
sbin/ipf/ipftest/md5.c
209
FF ( d, a, b, c, in[ 1], S12, UL(3905402710)); /* 2 */
sbin/ipf/ipftest/md5.c
210
FF ( c, d, a, b, in[ 2], S13, UL( 606105819)); /* 3 */
sbin/ipf/ipftest/md5.c
211
FF ( b, c, d, a, in[ 3], S14, UL(3250441966)); /* 4 */
sbin/ipf/ipftest/md5.c
212
FF ( a, b, c, d, in[ 4], S11, UL(4118548399)); /* 5 */
sbin/ipf/ipftest/md5.c
213
FF ( d, a, b, c, in[ 5], S12, UL(1200080426)); /* 6 */
sbin/ipf/ipftest/md5.c
214
FF ( c, d, a, b, in[ 6], S13, UL(2821735955)); /* 7 */
sbin/ipf/ipftest/md5.c
215
FF ( b, c, d, a, in[ 7], S14, UL(4249261313)); /* 8 */
sbin/ipf/ipftest/md5.c
216
FF ( a, b, c, d, in[ 8], S11, UL(1770035416)); /* 9 */
sbin/ipf/ipftest/md5.c
217
FF ( d, a, b, c, in[ 9], S12, UL(2336552879)); /* 10 */
sbin/ipf/ipftest/md5.c
218
FF ( c, d, a, b, in[10], S13, UL(4294925233)); /* 11 */
sbin/ipf/ipftest/md5.c
219
FF ( b, c, d, a, in[11], S14, UL(2304563134)); /* 12 */
sbin/ipf/ipftest/md5.c
220
FF ( a, b, c, d, in[12], S11, UL(1804603682)); /* 13 */
sbin/ipf/ipftest/md5.c
221
FF ( d, a, b, c, in[13], S12, UL(4254626195)); /* 14 */
sbin/ipf/ipftest/md5.c
222
FF ( c, d, a, b, in[14], S13, UL(2792965006)); /* 15 */
sbin/ipf/ipftest/md5.c
223
FF ( b, c, d, a, in[15], S14, UL(1236535329)); /* 16 */
sbin/ipf/ipftest/md5.c
230
GG ( a, b, c, d, in[ 1], S21, UL(4129170786)); /* 17 */
sbin/ipf/ipftest/md5.c
231
GG ( d, a, b, c, in[ 6], S22, UL(3225465664)); /* 18 */
sbin/ipf/ipftest/md5.c
232
GG ( c, d, a, b, in[11], S23, UL( 643717713)); /* 19 */
sbin/ipf/ipftest/md5.c
233
GG ( b, c, d, a, in[ 0], S24, UL(3921069994)); /* 20 */
sbin/ipf/ipftest/md5.c
234
GG ( a, b, c, d, in[ 5], S21, UL(3593408605)); /* 21 */
sbin/ipf/ipftest/md5.c
235
GG ( d, a, b, c, in[10], S22, UL( 38016083)); /* 22 */
sbin/ipf/ipftest/md5.c
236
GG ( c, d, a, b, in[15], S23, UL(3634488961)); /* 23 */
sbin/ipf/ipftest/md5.c
237
GG ( b, c, d, a, in[ 4], S24, UL(3889429448)); /* 24 */
sbin/ipf/ipftest/md5.c
238
GG ( a, b, c, d, in[ 9], S21, UL( 568446438)); /* 25 */
sbin/ipf/ipftest/md5.c
239
GG ( d, a, b, c, in[14], S22, UL(3275163606)); /* 26 */
sbin/ipf/ipftest/md5.c
240
GG ( c, d, a, b, in[ 3], S23, UL(4107603335)); /* 27 */
sbin/ipf/ipftest/md5.c
241
GG ( b, c, d, a, in[ 8], S24, UL(1163531501)); /* 28 */
sbin/ipf/ipftest/md5.c
242
GG ( a, b, c, d, in[13], S21, UL(2850285829)); /* 29 */
sbin/ipf/ipftest/md5.c
243
GG ( d, a, b, c, in[ 2], S22, UL(4243563512)); /* 30 */
sbin/ipf/ipftest/md5.c
244
GG ( c, d, a, b, in[ 7], S23, UL(1735328473)); /* 31 */
sbin/ipf/ipftest/md5.c
245
GG ( b, c, d, a, in[12], S24, UL(2368359562)); /* 32 */
sbin/ipf/ipftest/md5.c
252
HH ( a, b, c, d, in[ 5], S31, UL(4294588738)); /* 33 */
sbin/ipf/ipftest/md5.c
253
HH ( d, a, b, c, in[ 8], S32, UL(2272392833)); /* 34 */
sbin/ipf/ipftest/md5.c
254
HH ( c, d, a, b, in[11], S33, UL(1839030562)); /* 35 */
sbin/ipf/ipftest/md5.c
255
HH ( b, c, d, a, in[14], S34, UL(4259657740)); /* 36 */
sbin/ipf/ipftest/md5.c
256
HH ( a, b, c, d, in[ 1], S31, UL(2763975236)); /* 37 */
sbin/ipf/ipftest/md5.c
257
HH ( d, a, b, c, in[ 4], S32, UL(1272893353)); /* 38 */
sbin/ipf/ipftest/md5.c
258
HH ( c, d, a, b, in[ 7], S33, UL(4139469664)); /* 39 */
sbin/ipf/ipftest/md5.c
259
HH ( b, c, d, a, in[10], S34, UL(3200236656)); /* 40 */
sbin/ipf/ipftest/md5.c
260
HH ( a, b, c, d, in[13], S31, UL( 681279174)); /* 41 */
sbin/ipf/ipftest/md5.c
261
HH ( d, a, b, c, in[ 0], S32, UL(3936430074)); /* 42 */
sbin/ipf/ipftest/md5.c
262
HH ( c, d, a, b, in[ 3], S33, UL(3572445317)); /* 43 */
sbin/ipf/ipftest/md5.c
263
HH ( b, c, d, a, in[ 6], S34, UL( 76029189)); /* 44 */
sbin/ipf/ipftest/md5.c
264
HH ( a, b, c, d, in[ 9], S31, UL(3654602809)); /* 45 */
sbin/ipf/ipftest/md5.c
265
HH ( d, a, b, c, in[12], S32, UL(3873151461)); /* 46 */
sbin/ipf/ipftest/md5.c
266
HH ( c, d, a, b, in[15], S33, UL( 530742520)); /* 47 */
sbin/ipf/ipftest/md5.c
267
HH ( b, c, d, a, in[ 2], S34, UL(3299628645)); /* 48 */
sbin/ipf/ipftest/md5.c
274
II ( a, b, c, d, in[ 0], S41, UL(4096336452)); /* 49 */
sbin/ipf/ipftest/md5.c
275
II ( d, a, b, c, in[ 7], S42, UL(1126891415)); /* 50 */
sbin/ipf/ipftest/md5.c
276
II ( c, d, a, b, in[14], S43, UL(2878612391)); /* 51 */
sbin/ipf/ipftest/md5.c
277
II ( b, c, d, a, in[ 5], S44, UL(4237533241)); /* 52 */
sbin/ipf/ipftest/md5.c
278
II ( a, b, c, d, in[12], S41, UL(1700485571)); /* 53 */
sbin/ipf/ipftest/md5.c
279
II ( d, a, b, c, in[ 3], S42, UL(2399980690)); /* 54 */
sbin/ipf/ipftest/md5.c
280
II ( c, d, a, b, in[10], S43, UL(4293915773)); /* 55 */
sbin/ipf/ipftest/md5.c
281
II ( b, c, d, a, in[ 1], S44, UL(2240044497)); /* 56 */
sbin/ipf/ipftest/md5.c
282
II ( a, b, c, d, in[ 8], S41, UL(1873313359)); /* 57 */
sbin/ipf/ipftest/md5.c
283
II ( d, a, b, c, in[15], S42, UL(4264355552)); /* 58 */
sbin/ipf/ipftest/md5.c
284
II ( c, d, a, b, in[ 6], S43, UL(2734768916)); /* 59 */
sbin/ipf/ipftest/md5.c
285
II ( b, c, d, a, in[13], S44, UL(1309151649)); /* 60 */
sbin/ipf/ipftest/md5.c
286
II ( a, b, c, d, in[ 4], S41, UL(4149444226)); /* 61 */
sbin/ipf/ipftest/md5.c
287
II ( d, a, b, c, in[11], S42, UL(3174756917)); /* 62 */
sbin/ipf/ipftest/md5.c
288
II ( c, d, a, b, in[ 2], S43, UL( 718787259)); /* 63 */
sbin/ipf/ipftest/md5.c
289
II ( b, c, d, a, in[ 9], S44, UL(3951481745)); /* 64 */
sys/arm64/include/_stdint.h
48
#define UINT64_C(c) (c ## UL)
sys/arm64/include/armreg.h
1000
#define ID_AA64ISAR0_TS_MASK (UL(0xf) << ID_AA64ISAR0_TS_SHIFT)
sys/arm64/include/armreg.h
1002
#define ID_AA64ISAR0_TS_NONE (UL(0x0) << ID_AA64ISAR0_TS_SHIFT)
sys/arm64/include/armreg.h
1003
#define ID_AA64ISAR0_TS_CondM_8_4 (UL(0x1) << ID_AA64ISAR0_TS_SHIFT)
sys/arm64/include/armreg.h
1004
#define ID_AA64ISAR0_TS_CondM_8_5 (UL(0x2) << ID_AA64ISAR0_TS_SHIFT)
sys/arm64/include/armreg.h
1007
#define ID_AA64ISAR0_TLB_MASK (UL(0xf) << ID_AA64ISAR0_TLB_SHIFT)
sys/arm64/include/armreg.h
1009
#define ID_AA64ISAR0_TLB_NONE (UL(0x0) << ID_AA64ISAR0_TLB_SHIFT)
sys/arm64/include/armreg.h
1010
#define ID_AA64ISAR0_TLB_TLBIOS (UL(0x1) << ID_AA64ISAR0_TLB_SHIFT)
sys/arm64/include/armreg.h
1011
#define ID_AA64ISAR0_TLB_TLBIOSR (UL(0x2) << ID_AA64ISAR0_TLB_SHIFT)
sys/arm64/include/armreg.h
1014
#define ID_AA64ISAR0_RNDR_MASK (UL(0xf) << ID_AA64ISAR0_RNDR_SHIFT)
sys/arm64/include/armreg.h
1016
#define ID_AA64ISAR0_RNDR_NONE (UL(0x0) << ID_AA64ISAR0_RNDR_SHIFT)
sys/arm64/include/armreg.h
1017
#define ID_AA64ISAR0_RNDR_IMPL (UL(0x1) << ID_AA64ISAR0_RNDR_SHIFT)
sys/arm64/include/armreg.h
1029
#define ID_AA64ISAR1_DPB_MASK (UL(0xf) << ID_AA64ISAR1_DPB_SHIFT)
sys/arm64/include/armreg.h
1031
#define ID_AA64ISAR1_DPB_NONE (UL(0x0) << ID_AA64ISAR1_DPB_SHIFT)
sys/arm64/include/armreg.h
1032
#define ID_AA64ISAR1_DPB_DCCVAP (UL(0x1) << ID_AA64ISAR1_DPB_SHIFT)
sys/arm64/include/armreg.h
1033
#define ID_AA64ISAR1_DPB_DCCVADP (UL(0x2) << ID_AA64ISAR1_DPB_SHIFT)
sys/arm64/include/armreg.h
1036
#define ID_AA64ISAR1_APA_MASK (UL(0xf) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1038
#define ID_AA64ISAR1_APA_NONE (UL(0x0) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1039
#define ID_AA64ISAR1_APA_PAC (UL(0x1) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1040
#define ID_AA64ISAR1_APA_EPAC (UL(0x2) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1041
#define ID_AA64ISAR1_APA_EPAC2 (UL(0x3) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1042
#define ID_AA64ISAR1_APA_FPAC (UL(0x4) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1043
#define ID_AA64ISAR1_APA_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_APA_SHIFT)
sys/arm64/include/armreg.h
1046
#define ID_AA64ISAR1_API_MASK (UL(0xf) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1048
#define ID_AA64ISAR1_API_NONE (UL(0x0) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1049
#define ID_AA64ISAR1_API_PAC (UL(0x1) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1050
#define ID_AA64ISAR1_API_EPAC (UL(0x2) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1051
#define ID_AA64ISAR1_API_EPAC2 (UL(0x3) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1052
#define ID_AA64ISAR1_API_FPAC (UL(0x4) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1053
#define ID_AA64ISAR1_API_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR1_API_SHIFT)
sys/arm64/include/armreg.h
1056
#define ID_AA64ISAR1_JSCVT_MASK (UL(0xf) << ID_AA64ISAR1_JSCVT_SHIFT)
sys/arm64/include/armreg.h
1058
#define ID_AA64ISAR1_JSCVT_NONE (UL(0x0) << ID_AA64ISAR1_JSCVT_SHIFT)
sys/arm64/include/armreg.h
1059
#define ID_AA64ISAR1_JSCVT_IMPL (UL(0x1) << ID_AA64ISAR1_JSCVT_SHIFT)
sys/arm64/include/armreg.h
1062
#define ID_AA64ISAR1_FCMA_MASK (UL(0xf) << ID_AA64ISAR1_FCMA_SHIFT)
sys/arm64/include/armreg.h
1064
#define ID_AA64ISAR1_FCMA_NONE (UL(0x0) << ID_AA64ISAR1_FCMA_SHIFT)
sys/arm64/include/armreg.h
1065
#define ID_AA64ISAR1_FCMA_IMPL (UL(0x1) << ID_AA64ISAR1_FCMA_SHIFT)
sys/arm64/include/armreg.h
1068
#define ID_AA64ISAR1_LRCPC_MASK (UL(0xf) << ID_AA64ISAR1_LRCPC_SHIFT)
sys/arm64/include/armreg.h
1070
#define ID_AA64ISAR1_LRCPC_NONE (UL(0x0) << ID_AA64ISAR1_LRCPC_SHIFT)
sys/arm64/include/armreg.h
1071
#define ID_AA64ISAR1_LRCPC_RCPC_8_3 (UL(0x1) << ID_AA64ISAR1_LRCPC_SHIFT)
sys/arm64/include/armreg.h
1072
#define ID_AA64ISAR1_LRCPC_RCPC_8_4 (UL(0x2) << ID_AA64ISAR1_LRCPC_SHIFT)
sys/arm64/include/armreg.h
1075
#define ID_AA64ISAR1_GPA_MASK (UL(0xf) << ID_AA64ISAR1_GPA_SHIFT)
sys/arm64/include/armreg.h
1077
#define ID_AA64ISAR1_GPA_NONE (UL(0x0) << ID_AA64ISAR1_GPA_SHIFT)
sys/arm64/include/armreg.h
1078
#define ID_AA64ISAR1_GPA_IMPL (UL(0x1) << ID_AA64ISAR1_GPA_SHIFT)
sys/arm64/include/armreg.h
1081
#define ID_AA64ISAR1_GPI_MASK (UL(0xf) << ID_AA64ISAR1_GPI_SHIFT)
sys/arm64/include/armreg.h
1083
#define ID_AA64ISAR1_GPI_NONE (UL(0x0) << ID_AA64ISAR1_GPI_SHIFT)
sys/arm64/include/armreg.h
1084
#define ID_AA64ISAR1_GPI_IMPL (UL(0x1) << ID_AA64ISAR1_GPI_SHIFT)
sys/arm64/include/armreg.h
1087
#define ID_AA64ISAR1_FRINTTS_MASK (UL(0xf) << ID_AA64ISAR1_FRINTTS_SHIFT)
sys/arm64/include/armreg.h
1089
#define ID_AA64ISAR1_FRINTTS_NONE (UL(0x0) << ID_AA64ISAR1_FRINTTS_SHIFT)
sys/arm64/include/armreg.h
1090
#define ID_AA64ISAR1_FRINTTS_IMPL (UL(0x1) << ID_AA64ISAR1_FRINTTS_SHIFT)
sys/arm64/include/armreg.h
1093
#define ID_AA64ISAR1_SB_MASK (UL(0xf) << ID_AA64ISAR1_SB_SHIFT)
sys/arm64/include/armreg.h
1095
#define ID_AA64ISAR1_SB_NONE (UL(0x0) << ID_AA64ISAR1_SB_SHIFT)
sys/arm64/include/armreg.h
1096
#define ID_AA64ISAR1_SB_IMPL (UL(0x1) << ID_AA64ISAR1_SB_SHIFT)
sys/arm64/include/armreg.h
1099
#define ID_AA64ISAR1_SPECRES_MASK (UL(0xf) << ID_AA64ISAR1_SPECRES_SHIFT)
sys/arm64/include/armreg.h
1101
#define ID_AA64ISAR1_SPECRES_NONE (UL(0x0) << ID_AA64ISAR1_SPECRES_SHIFT)
sys/arm64/include/armreg.h
1102
#define ID_AA64ISAR1_SPECRES_8_5 (UL(0x1) << ID_AA64ISAR1_SPECRES_SHIFT)
sys/arm64/include/armreg.h
1103
#define ID_AA64ISAR1_SPECRES_8_9 (UL(0x2) << ID_AA64ISAR1_SPECRES_SHIFT)
sys/arm64/include/armreg.h
1106
#define ID_AA64ISAR1_BF16_MASK (UL(0xf) << ID_AA64ISAR1_BF16_SHIFT)
sys/arm64/include/armreg.h
1108
#define ID_AA64ISAR1_BF16_NONE (UL(0x0) << ID_AA64ISAR1_BF16_SHIFT)
sys/arm64/include/armreg.h
1109
#define ID_AA64ISAR1_BF16_IMPL (UL(0x1) << ID_AA64ISAR1_BF16_SHIFT)
sys/arm64/include/armreg.h
1110
#define ID_AA64ISAR1_BF16_EBF (UL(0x2) << ID_AA64ISAR1_BF16_SHIFT)
sys/arm64/include/armreg.h
1113
#define ID_AA64ISAR1_DGH_MASK (UL(0xf) << ID_AA64ISAR1_DGH_SHIFT)
sys/arm64/include/armreg.h
1115
#define ID_AA64ISAR1_DGH_NONE (UL(0x0) << ID_AA64ISAR1_DGH_SHIFT)
sys/arm64/include/armreg.h
1116
#define ID_AA64ISAR1_DGH_IMPL (UL(0x1) << ID_AA64ISAR1_DGH_SHIFT)
sys/arm64/include/armreg.h
1119
#define ID_AA64ISAR1_I8MM_MASK (UL(0xf) << ID_AA64ISAR1_I8MM_SHIFT)
sys/arm64/include/armreg.h
1121
#define ID_AA64ISAR1_I8MM_NONE (UL(0x0) << ID_AA64ISAR1_I8MM_SHIFT)
sys/arm64/include/armreg.h
1122
#define ID_AA64ISAR1_I8MM_IMPL (UL(0x1) << ID_AA64ISAR1_I8MM_SHIFT)
sys/arm64/include/armreg.h
1125
#define ID_AA64ISAR1_XS_MASK (UL(0xf) << ID_AA64ISAR1_XS_SHIFT)
sys/arm64/include/armreg.h
1127
#define ID_AA64ISAR1_XS_NONE (UL(0x0) << ID_AA64ISAR1_XS_SHIFT)
sys/arm64/include/armreg.h
1128
#define ID_AA64ISAR1_XS_IMPL (UL(0x1) << ID_AA64ISAR1_XS_SHIFT)
sys/arm64/include/armreg.h
1131
#define ID_AA64ISAR1_LS64_MASK (UL(0xf) << ID_AA64ISAR1_LS64_SHIFT)
sys/arm64/include/armreg.h
1133
#define ID_AA64ISAR1_LS64_NONE (UL(0x0) << ID_AA64ISAR1_LS64_SHIFT)
sys/arm64/include/armreg.h
1134
#define ID_AA64ISAR1_LS64_IMPL (UL(0x1) << ID_AA64ISAR1_LS64_SHIFT)
sys/arm64/include/armreg.h
1135
#define ID_AA64ISAR1_LS64_V (UL(0x2) << ID_AA64ISAR1_LS64_SHIFT)
sys/arm64/include/armreg.h
1136
#define ID_AA64ISAR1_LS64_ACCDATA (UL(0x3) << ID_AA64ISAR1_LS64_SHIFT)
sys/arm64/include/armreg.h
1148
#define ID_AA64ISAR2_WFxT_MASK (UL(0xf) << ID_AA64ISAR2_WFxT_SHIFT)
sys/arm64/include/armreg.h
1150
#define ID_AA64ISAR2_WFxT_NONE (UL(0x0) << ID_AA64ISAR2_WFxT_SHIFT)
sys/arm64/include/armreg.h
1151
#define ID_AA64ISAR2_WFxT_IMPL (UL(0x2) << ID_AA64ISAR2_WFxT_SHIFT)
sys/arm64/include/armreg.h
1154
#define ID_AA64ISAR2_RPRES_MASK (UL(0xf) << ID_AA64ISAR2_RPRES_SHIFT)
sys/arm64/include/armreg.h
1156
#define ID_AA64ISAR2_RPRES_NONE (UL(0x0) << ID_AA64ISAR2_RPRES_SHIFT)
sys/arm64/include/armreg.h
1157
#define ID_AA64ISAR2_RPRES_IMPL (UL(0x1) << ID_AA64ISAR2_RPRES_SHIFT)
sys/arm64/include/armreg.h
1160
#define ID_AA64ISAR2_GPA3_MASK (UL(0xf) << ID_AA64ISAR2_GPA3_SHIFT)
sys/arm64/include/armreg.h
1162
#define ID_AA64ISAR2_GPA3_NONE (UL(0x0) << ID_AA64ISAR2_GPA3_SHIFT)
sys/arm64/include/armreg.h
1163
#define ID_AA64ISAR2_GPA3_IMPL (UL(0x1) << ID_AA64ISAR2_GPA3_SHIFT)
sys/arm64/include/armreg.h
1166
#define ID_AA64ISAR2_APA3_MASK (UL(0xf) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1168
#define ID_AA64ISAR2_APA3_NONE (UL(0x0) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1169
#define ID_AA64ISAR2_APA3_PAC (UL(0x1) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1170
#define ID_AA64ISAR2_APA3_EPAC (UL(0x2) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1171
#define ID_AA64ISAR2_APA3_EPAC2 (UL(0x3) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1172
#define ID_AA64ISAR2_APA3_FPAC (UL(0x4) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1173
#define ID_AA64ISAR2_APA3_FPAC_COMBINED (UL(0x5) << ID_AA64ISAR2_APA3_SHIFT)
sys/arm64/include/armreg.h
1176
#define ID_AA64ISAR2_MOPS_MASK (UL(0xf) << ID_AA64ISAR2_MOPS_SHIFT)
sys/arm64/include/armreg.h
1178
#define ID_AA64ISAR2_MOPS_NONE (UL(0x0) << ID_AA64ISAR2_MOPS_SHIFT)
sys/arm64/include/armreg.h
1179
#define ID_AA64ISAR2_MOPS_IMPL (UL(0x1) << ID_AA64ISAR2_MOPS_SHIFT)
sys/arm64/include/armreg.h
1182
#define ID_AA64ISAR2_BC_MASK (UL(0xf) << ID_AA64ISAR2_BC_SHIFT)
sys/arm64/include/armreg.h
1184
#define ID_AA64ISAR2_BC_NONE (UL(0x0) << ID_AA64ISAR2_BC_SHIFT)
sys/arm64/include/armreg.h
1185
#define ID_AA64ISAR2_BC_IMPL (UL(0x1) << ID_AA64ISAR2_BC_SHIFT)
sys/arm64/include/armreg.h
1188
#define ID_AA64ISAR2_PAC_frac_MASK (UL(0xf) << ID_AA64ISAR2_PAC_frac_SHIFT)
sys/arm64/include/armreg.h
1190
#define ID_AA64ISAR2_PAC_frac_NONE (UL(0x0) << ID_AA64ISAR2_PAC_frac_SHIFT)
sys/arm64/include/armreg.h
1191
#define ID_AA64ISAR2_PAC_frac_IMPL (UL(0x1) << ID_AA64ISAR2_PAC_frac_SHIFT)
sys/arm64/include/armreg.h
1194
#define ID_AA64ISAR2_CLRBHB_MASK (UL(0xf) << ID_AA64ISAR2_CLRBHB_SHIFT)
sys/arm64/include/armreg.h
1196
#define ID_AA64ISAR2_CLRBHB_NONE (UL(0x0) << ID_AA64ISAR2_CLRBHB_SHIFT)
sys/arm64/include/armreg.h
1197
#define ID_AA64ISAR2_CLRBHB_IMPL (UL(0x1) << ID_AA64ISAR2_CLRBHB_SHIFT)
sys/arm64/include/armreg.h
1200
#define ID_AA64ISAR2_PRFMSLC_MASK (UL(0xf) << ID_AA64ISAR2_PRFMSLC_SHIFT)
sys/arm64/include/armreg.h
1202
#define ID_AA64ISAR2_PRFMSLC_NONE (UL(0x0) << ID_AA64ISAR2_PRFMSLC_SHIFT)
sys/arm64/include/armreg.h
1203
#define ID_AA64ISAR2_PRFMSLC_IMPL (UL(0x1) << ID_AA64ISAR2_PRFMSLC_SHIFT)
sys/arm64/include/armreg.h
1206
#define ID_AA64ISAR2_RPRFM_MASK (UL(0xf) << ID_AA64ISAR2_RPRFM_SHIFT)
sys/arm64/include/armreg.h
1208
#define ID_AA64ISAR2_RPRFM_NONE (UL(0x0) << ID_AA64ISAR2_RPRFM_SHIFT)
sys/arm64/include/armreg.h
1209
#define ID_AA64ISAR2_RPRFM_IMPL (UL(0x1) << ID_AA64ISAR2_RPRFM_SHIFT)
sys/arm64/include/armreg.h
1212
#define ID_AA64ISAR2_CSSC_MASK (UL(0xf) << ID_AA64ISAR2_CSSC_SHIFT)
sys/arm64/include/armreg.h
1214
#define ID_AA64ISAR2_CSSC_NONE (UL(0x0) << ID_AA64ISAR2_CSSC_SHIFT)
sys/arm64/include/armreg.h
1215
#define ID_AA64ISAR2_CSSC_IMPL (UL(0x1) << ID_AA64ISAR2_CSSC_SHIFT)
sys/arm64/include/armreg.h
1218
#define ID_AA64ISAR2_ATS1A_MASK (UL(0xf) << ID_AA64ISAR2_ATS1A_SHIFT)
sys/arm64/include/armreg.h
1220
#define ID_AA64ISAR2_ATS1A_NONE (UL(0x0) << ID_AA64ISAR2_ATS1A_SHIFT)
sys/arm64/include/armreg.h
1221
#define ID_AA64ISAR2_ATS1A_IMPL (UL(0x1) << ID_AA64ISAR2_ATS1A_SHIFT)
sys/arm64/include/armreg.h
1233
#define ID_AA64MMFR0_PARange_MASK (UL(0xf) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1235
#define ID_AA64MMFR0_PARange_4G (UL(0x0) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1236
#define ID_AA64MMFR0_PARange_64G (UL(0x1) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1237
#define ID_AA64MMFR0_PARange_1T (UL(0x2) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1238
#define ID_AA64MMFR0_PARange_4T (UL(0x3) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1239
#define ID_AA64MMFR0_PARange_16T (UL(0x4) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1240
#define ID_AA64MMFR0_PARange_256T (UL(0x5) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1241
#define ID_AA64MMFR0_PARange_4P (UL(0x6) << ID_AA64MMFR0_PARange_SHIFT)
sys/arm64/include/armreg.h
1244
#define ID_AA64MMFR0_ASIDBits_MASK (UL(0xf) << ID_AA64MMFR0_ASIDBits_SHIFT)
sys/arm64/include/armreg.h
1246
#define ID_AA64MMFR0_ASIDBits_8 (UL(0x0) << ID_AA64MMFR0_ASIDBits_SHIFT)
sys/arm64/include/armreg.h
1247
#define ID_AA64MMFR0_ASIDBits_16 (UL(0x2) << ID_AA64MMFR0_ASIDBits_SHIFT)
sys/arm64/include/armreg.h
1250
#define ID_AA64MMFR0_BigEnd_MASK (UL(0xf) << ID_AA64MMFR0_BigEnd_SHIFT)
sys/arm64/include/armreg.h
1252
#define ID_AA64MMFR0_BigEnd_FIXED (UL(0x0) << ID_AA64MMFR0_BigEnd_SHIFT)
sys/arm64/include/armreg.h
1253
#define ID_AA64MMFR0_BigEnd_MIXED (UL(0x1) << ID_AA64MMFR0_BigEnd_SHIFT)
sys/arm64/include/armreg.h
1256
#define ID_AA64MMFR0_SNSMem_MASK (UL(0xf) << ID_AA64MMFR0_SNSMem_SHIFT)
sys/arm64/include/armreg.h
1258
#define ID_AA64MMFR0_SNSMem_NONE (UL(0x0) << ID_AA64MMFR0_SNSMem_SHIFT)
sys/arm64/include/armreg.h
1259
#define ID_AA64MMFR0_SNSMem_DISTINCT (UL(0x1) << ID_AA64MMFR0_SNSMem_SHIFT)
sys/arm64/include/armreg.h
1262
#define ID_AA64MMFR0_BigEndEL0_MASK (UL(0xf) << ID_AA64MMFR0_BigEndEL0_SHIFT)
sys/arm64/include/armreg.h
1264
#define ID_AA64MMFR0_BigEndEL0_FIXED (UL(0x0) << ID_AA64MMFR0_BigEndEL0_SHIFT)
sys/arm64/include/armreg.h
1265
#define ID_AA64MMFR0_BigEndEL0_MIXED (UL(0x1) << ID_AA64MMFR0_BigEndEL0_SHIFT)
sys/arm64/include/armreg.h
1268
#define ID_AA64MMFR0_TGran16_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_SHIFT)
sys/arm64/include/armreg.h
1270
#define ID_AA64MMFR0_TGran16_NONE (UL(0x0) << ID_AA64MMFR0_TGran16_SHIFT)
sys/arm64/include/armreg.h
1271
#define ID_AA64MMFR0_TGran16_IMPL (UL(0x1) << ID_AA64MMFR0_TGran16_SHIFT)
sys/arm64/include/armreg.h
1272
#define ID_AA64MMFR0_TGran16_LPA2 (UL(0x2) << ID_AA64MMFR0_TGran16_SHIFT)
sys/arm64/include/armreg.h
1275
#define ID_AA64MMFR0_TGran64_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
sys/arm64/include/armreg.h
1277
#define ID_AA64MMFR0_TGran64_IMPL (UL(0x0) << ID_AA64MMFR0_TGran64_SHIFT)
sys/arm64/include/armreg.h
1278
#define ID_AA64MMFR0_TGran64_NONE (UL(0xf) << ID_AA64MMFR0_TGran64_SHIFT)
sys/arm64/include/armreg.h
1281
#define ID_AA64MMFR0_TGran4_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
sys/arm64/include/armreg.h
1283
#define ID_AA64MMFR0_TGran4_IMPL (UL(0x0) << ID_AA64MMFR0_TGran4_SHIFT)
sys/arm64/include/armreg.h
1284
#define ID_AA64MMFR0_TGran4_LPA2 (UL(0x1) << ID_AA64MMFR0_TGran4_SHIFT)
sys/arm64/include/armreg.h
1285
#define ID_AA64MMFR0_TGran4_NONE (UL(0xf) << ID_AA64MMFR0_TGran4_SHIFT)
sys/arm64/include/armreg.h
1288
#define ID_AA64MMFR0_TGran16_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran16_2_SHIFT)
sys/arm64/include/armreg.h
1290
#define ID_AA64MMFR0_TGran16_2_TGran16 (UL(0x0) << ID_AA64MMFR0_TGran16_2_SHIFT)
sys/arm64/include/armreg.h
1291
#define ID_AA64MMFR0_TGran16_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran16_2_SHIFT)
sys/arm64/include/armreg.h
1292
#define ID_AA64MMFR0_TGran16_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran16_2_SHIFT)
sys/arm64/include/armreg.h
1293
#define ID_AA64MMFR0_TGran16_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran16_2_SHIFT)
sys/arm64/include/armreg.h
1296
#define ID_AA64MMFR0_TGran64_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran64_2_SHIFT)
sys/arm64/include/armreg.h
1298
#define ID_AA64MMFR0_TGran64_2_TGran64 (UL(0x0) << ID_AA64MMFR0_TGran64_2_SHIFT)
sys/arm64/include/armreg.h
1299
#define ID_AA64MMFR0_TGran64_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran64_2_SHIFT)
sys/arm64/include/armreg.h
1300
#define ID_AA64MMFR0_TGran64_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran64_2_SHIFT)
sys/arm64/include/armreg.h
1303
#define ID_AA64MMFR0_TGran4_2_MASK (UL(0xf) << ID_AA64MMFR0_TGran4_2_SHIFT)
sys/arm64/include/armreg.h
1305
#define ID_AA64MMFR0_TGran4_2_TGran4 (UL(0x0) << ID_AA64MMFR0_TGran4_2_SHIFT)
sys/arm64/include/armreg.h
1306
#define ID_AA64MMFR0_TGran4_2_NONE (UL(0x1) << ID_AA64MMFR0_TGran4_2_SHIFT)
sys/arm64/include/armreg.h
1307
#define ID_AA64MMFR0_TGran4_2_IMPL (UL(0x2) << ID_AA64MMFR0_TGran4_2_SHIFT)
sys/arm64/include/armreg.h
1308
#define ID_AA64MMFR0_TGran4_2_LPA2 (UL(0x3) << ID_AA64MMFR0_TGran4_2_SHIFT)
sys/arm64/include/armreg.h
1311
#define ID_AA64MMFR0_ExS_MASK (UL(0xf) << ID_AA64MMFR0_ExS_SHIFT)
sys/arm64/include/armreg.h
1313
#define ID_AA64MMFR0_ExS_ALL (UL(0x0) << ID_AA64MMFR0_ExS_SHIFT)
sys/arm64/include/armreg.h
1314
#define ID_AA64MMFR0_ExS_IMPL (UL(0x1) << ID_AA64MMFR0_ExS_SHIFT)
sys/arm64/include/armreg.h
1317
#define ID_AA64MMFR0_FGT_MASK (UL(0xf) << ID_AA64MMFR0_FGT_SHIFT)
sys/arm64/include/armreg.h
1319
#define ID_AA64MMFR0_FGT_NONE (UL(0x0) << ID_AA64MMFR0_FGT_SHIFT)
sys/arm64/include/armreg.h
1320
#define ID_AA64MMFR0_FGT_8_6 (UL(0x1) << ID_AA64MMFR0_FGT_SHIFT)
sys/arm64/include/armreg.h
1321
#define ID_AA64MMFR0_FGT_8_9 (UL(0x2) << ID_AA64MMFR0_FGT_SHIFT)
sys/arm64/include/armreg.h
1324
#define ID_AA64MMFR0_ECV_MASK (UL(0xf) << ID_AA64MMFR0_ECV_SHIFT)
sys/arm64/include/armreg.h
1326
#define ID_AA64MMFR0_ECV_NONE (UL(0x0) << ID_AA64MMFR0_ECV_SHIFT)
sys/arm64/include/armreg.h
1327
#define ID_AA64MMFR0_ECV_IMPL (UL(0x1) << ID_AA64MMFR0_ECV_SHIFT)
sys/arm64/include/armreg.h
1328
#define ID_AA64MMFR0_ECV_POFF (UL(0x2) << ID_AA64MMFR0_ECV_SHIFT)
sys/arm64/include/armreg.h
1340
#define ID_AA64MMFR1_HAFDBS_MASK (UL(0xf) << ID_AA64MMFR1_HAFDBS_SHIFT)
sys/arm64/include/armreg.h
1342
#define ID_AA64MMFR1_HAFDBS_NONE (UL(0x0) << ID_AA64MMFR1_HAFDBS_SHIFT)
sys/arm64/include/armreg.h
1343
#define ID_AA64MMFR1_HAFDBS_AF (UL(0x1) << ID_AA64MMFR1_HAFDBS_SHIFT)
sys/arm64/include/armreg.h
1344
#define ID_AA64MMFR1_HAFDBS_AF_DBS (UL(0x2) << ID_AA64MMFR1_HAFDBS_SHIFT)
sys/arm64/include/armreg.h
1347
#define ID_AA64MMFR1_VMIDBits_MASK (UL(0xf) << ID_AA64MMFR1_VMIDBits_SHIFT)
sys/arm64/include/armreg.h
1349
#define ID_AA64MMFR1_VMIDBits_8 (UL(0x0) << ID_AA64MMFR1_VMIDBits_SHIFT)
sys/arm64/include/armreg.h
1350
#define ID_AA64MMFR1_VMIDBits_16 (UL(0x2) << ID_AA64MMFR1_VMIDBits_SHIFT)
sys/arm64/include/armreg.h
1353
#define ID_AA64MMFR1_VH_MASK (UL(0xf) << ID_AA64MMFR1_VH_SHIFT)
sys/arm64/include/armreg.h
1355
#define ID_AA64MMFR1_VH_NONE (UL(0x0) << ID_AA64MMFR1_VH_SHIFT)
sys/arm64/include/armreg.h
1356
#define ID_AA64MMFR1_VH_IMPL (UL(0x1) << ID_AA64MMFR1_VH_SHIFT)
sys/arm64/include/armreg.h
1359
#define ID_AA64MMFR1_HPDS_MASK (UL(0xf) << ID_AA64MMFR1_HPDS_SHIFT)
sys/arm64/include/armreg.h
1361
#define ID_AA64MMFR1_HPDS_NONE (UL(0x0) << ID_AA64MMFR1_HPDS_SHIFT)
sys/arm64/include/armreg.h
1362
#define ID_AA64MMFR1_HPDS_HPD (UL(0x1) << ID_AA64MMFR1_HPDS_SHIFT)
sys/arm64/include/armreg.h
1363
#define ID_AA64MMFR1_HPDS_TTPBHA (UL(0x2) << ID_AA64MMFR1_HPDS_SHIFT)
sys/arm64/include/armreg.h
1366
#define ID_AA64MMFR1_LO_MASK (UL(0xf) << ID_AA64MMFR1_LO_SHIFT)
sys/arm64/include/armreg.h
1368
#define ID_AA64MMFR1_LO_NONE (UL(0x0) << ID_AA64MMFR1_LO_SHIFT)
sys/arm64/include/armreg.h
1369
#define ID_AA64MMFR1_LO_IMPL (UL(0x1) << ID_AA64MMFR1_LO_SHIFT)
sys/arm64/include/armreg.h
1372
#define ID_AA64MMFR1_PAN_MASK (UL(0xf) << ID_AA64MMFR1_PAN_SHIFT)
sys/arm64/include/armreg.h
1374
#define ID_AA64MMFR1_PAN_NONE (UL(0x0) << ID_AA64MMFR1_PAN_SHIFT)
sys/arm64/include/armreg.h
1375
#define ID_AA64MMFR1_PAN_IMPL (UL(0x1) << ID_AA64MMFR1_PAN_SHIFT)
sys/arm64/include/armreg.h
1376
#define ID_AA64MMFR1_PAN_ATS1E1 (UL(0x2) << ID_AA64MMFR1_PAN_SHIFT)
sys/arm64/include/armreg.h
1377
#define ID_AA64MMFR1_PAN_EPAN (UL(0x3) << ID_AA64MMFR1_PAN_SHIFT)
sys/arm64/include/armreg.h
1380
#define ID_AA64MMFR1_SpecSEI_MASK (UL(0xf) << ID_AA64MMFR1_SpecSEI_SHIFT)
sys/arm64/include/armreg.h
1382
#define ID_AA64MMFR1_SpecSEI_NONE (UL(0x0) << ID_AA64MMFR1_SpecSEI_SHIFT)
sys/arm64/include/armreg.h
1383
#define ID_AA64MMFR1_SpecSEI_IMPL (UL(0x1) << ID_AA64MMFR1_SpecSEI_SHIFT)
sys/arm64/include/armreg.h
1386
#define ID_AA64MMFR1_XNX_MASK (UL(0xf) << ID_AA64MMFR1_XNX_SHIFT)
sys/arm64/include/armreg.h
1388
#define ID_AA64MMFR1_XNX_NONE (UL(0x0) << ID_AA64MMFR1_XNX_SHIFT)
sys/arm64/include/armreg.h
1389
#define ID_AA64MMFR1_XNX_IMPL (UL(0x1) << ID_AA64MMFR1_XNX_SHIFT)
sys/arm64/include/armreg.h
1392
#define ID_AA64MMFR1_TWED_MASK (UL(0xf) << ID_AA64MMFR1_TWED_SHIFT)
sys/arm64/include/armreg.h
1394
#define ID_AA64MMFR1_TWED_NONE (UL(0x0) << ID_AA64MMFR1_TWED_SHIFT)
sys/arm64/include/armreg.h
1395
#define ID_AA64MMFR1_TWED_IMPL (UL(0x1) << ID_AA64MMFR1_TWED_SHIFT)
sys/arm64/include/armreg.h
1398
#define ID_AA64MMFR1_ETS_MASK (UL(0xf) << ID_AA64MMFR1_ETS_SHIFT)
sys/arm64/include/armreg.h
1400
#define ID_AA64MMFR1_ETS_NONE (UL(0x0) << ID_AA64MMFR1_ETS_SHIFT)
sys/arm64/include/armreg.h
1401
#define ID_AA64MMFR1_ETS_NONE2 (UL(0x1) << ID_AA64MMFR1_ETS_SHIFT)
sys/arm64/include/armreg.h
1402
#define ID_AA64MMFR1_ETS_IMPL (UL(0x2) << ID_AA64MMFR1_ETS_SHIFT)
sys/arm64/include/armreg.h
1405
#define ID_AA64MMFR1_HCX_MASK (UL(0xf) << ID_AA64MMFR1_HCX_SHIFT)
sys/arm64/include/armreg.h
1407
#define ID_AA64MMFR1_HCX_NONE (UL(0x0) << ID_AA64MMFR1_HCX_SHIFT)
sys/arm64/include/armreg.h
1408
#define ID_AA64MMFR1_HCX_IMPL (UL(0x1) << ID_AA64MMFR1_HCX_SHIFT)
sys/arm64/include/armreg.h
1411
#define ID_AA64MMFR1_AFP_MASK (UL(0xf) << ID_AA64MMFR1_AFP_SHIFT)
sys/arm64/include/armreg.h
1413
#define ID_AA64MMFR1_AFP_NONE (UL(0x0) << ID_AA64MMFR1_AFP_SHIFT)
sys/arm64/include/armreg.h
1414
#define ID_AA64MMFR1_AFP_IMPL (UL(0x1) << ID_AA64MMFR1_AFP_SHIFT)
sys/arm64/include/armreg.h
1417
#define ID_AA64MMFR1_nTLBPA_MASK (UL(0xf) << ID_AA64MMFR1_nTLBPA_SHIFT)
sys/arm64/include/armreg.h
1419
#define ID_AA64MMFR1_nTLBPA_NONE (UL(0x0) << ID_AA64MMFR1_nTLBPA_SHIFT)
sys/arm64/include/armreg.h
1420
#define ID_AA64MMFR1_nTLBPA_IMPL (UL(0x1) << ID_AA64MMFR1_nTLBPA_SHIFT)
sys/arm64/include/armreg.h
1423
#define ID_AA64MMFR1_TIDCP1_MASK (UL(0xf) << ID_AA64MMFR1_TIDCP1_SHIFT)
sys/arm64/include/armreg.h
1425
#define ID_AA64MMFR1_TIDCP1_NONE (UL(0x0) << ID_AA64MMFR1_TIDCP1_SHIFT)
sys/arm64/include/armreg.h
1426
#define ID_AA64MMFR1_TIDCP1_IMPL (UL(0x1) << ID_AA64MMFR1_TIDCP1_SHIFT)
sys/arm64/include/armreg.h
1429
#define ID_AA64MMFR1_CMOVW_MASK (UL(0xf) << ID_AA64MMFR1_CMOVW_SHIFT)
sys/arm64/include/armreg.h
1431
#define ID_AA64MMFR1_CMOVW_NONE (UL(0x0) << ID_AA64MMFR1_CMOVW_SHIFT)
sys/arm64/include/armreg.h
1432
#define ID_AA64MMFR1_CMOVW_IMPL (UL(0x1) << ID_AA64MMFR1_CMOVW_SHIFT)
sys/arm64/include/armreg.h
1435
#define ID_AA64MMFR1_ECBHB_MASK (UL(0xf) << ID_AA64MMFR1_ECBHB_SHIFT)
sys/arm64/include/armreg.h
1437
#define ID_AA64MMFR1_ECBHB_NONE (UL(0x0) << ID_AA64MMFR1_ECBHB_SHIFT)
sys/arm64/include/armreg.h
1438
#define ID_AA64MMFR1_ECBHB_IMPL (UL(0x1) << ID_AA64MMFR1_ECBHB_SHIFT)
sys/arm64/include/armreg.h
1450
#define ID_AA64MMFR2_CnP_MASK (UL(0xf) << ID_AA64MMFR2_CnP_SHIFT)
sys/arm64/include/armreg.h
1452
#define ID_AA64MMFR2_CnP_NONE (UL(0x0) << ID_AA64MMFR2_CnP_SHIFT)
sys/arm64/include/armreg.h
1453
#define ID_AA64MMFR2_CnP_IMPL (UL(0x1) << ID_AA64MMFR2_CnP_SHIFT)
sys/arm64/include/armreg.h
1456
#define ID_AA64MMFR2_UAO_MASK (UL(0xf) << ID_AA64MMFR2_UAO_SHIFT)
sys/arm64/include/armreg.h
1458
#define ID_AA64MMFR2_UAO_NONE (UL(0x0) << ID_AA64MMFR2_UAO_SHIFT)
sys/arm64/include/armreg.h
1459
#define ID_AA64MMFR2_UAO_IMPL (UL(0x1) << ID_AA64MMFR2_UAO_SHIFT)
sys/arm64/include/armreg.h
1462
#define ID_AA64MMFR2_LSM_MASK (UL(0xf) << ID_AA64MMFR2_LSM_SHIFT)
sys/arm64/include/armreg.h
1464
#define ID_AA64MMFR2_LSM_NONE (UL(0x0) << ID_AA64MMFR2_LSM_SHIFT)
sys/arm64/include/armreg.h
1465
#define ID_AA64MMFR2_LSM_IMPL (UL(0x1) << ID_AA64MMFR2_LSM_SHIFT)
sys/arm64/include/armreg.h
1468
#define ID_AA64MMFR2_IESB_MASK (UL(0xf) << ID_AA64MMFR2_IESB_SHIFT)
sys/arm64/include/armreg.h
1470
#define ID_AA64MMFR2_IESB_NONE (UL(0x0) << ID_AA64MMFR2_IESB_SHIFT)
sys/arm64/include/armreg.h
1471
#define ID_AA64MMFR2_IESB_IMPL (UL(0x1) << ID_AA64MMFR2_IESB_SHIFT)
sys/arm64/include/armreg.h
1474
#define ID_AA64MMFR2_VARange_MASK (UL(0xf) << ID_AA64MMFR2_VARange_SHIFT)
sys/arm64/include/armreg.h
1476
#define ID_AA64MMFR2_VARange_48 (UL(0x0) << ID_AA64MMFR2_VARange_SHIFT)
sys/arm64/include/armreg.h
1477
#define ID_AA64MMFR2_VARange_52 (UL(0x1) << ID_AA64MMFR2_VARange_SHIFT)
sys/arm64/include/armreg.h
1480
#define ID_AA64MMFR2_CCIDX_MASK (UL(0xf) << ID_AA64MMFR2_CCIDX_SHIFT)
sys/arm64/include/armreg.h
1482
#define ID_AA64MMFR2_CCIDX_32 (UL(0x0) << ID_AA64MMFR2_CCIDX_SHIFT)
sys/arm64/include/armreg.h
1483
#define ID_AA64MMFR2_CCIDX_64 (UL(0x1) << ID_AA64MMFR2_CCIDX_SHIFT)
sys/arm64/include/armreg.h
1486
#define ID_AA64MMFR2_NV_MASK (UL(0xf) << ID_AA64MMFR2_NV_SHIFT)
sys/arm64/include/armreg.h
1488
#define ID_AA64MMFR2_NV_NONE (UL(0x0) << ID_AA64MMFR2_NV_SHIFT)
sys/arm64/include/armreg.h
1489
#define ID_AA64MMFR2_NV_8_3 (UL(0x1) << ID_AA64MMFR2_NV_SHIFT)
sys/arm64/include/armreg.h
1490
#define ID_AA64MMFR2_NV_8_4 (UL(0x2) << ID_AA64MMFR2_NV_SHIFT)
sys/arm64/include/armreg.h
1493
#define ID_AA64MMFR2_ST_MASK (UL(0xf) << ID_AA64MMFR2_ST_SHIFT)
sys/arm64/include/armreg.h
1495
#define ID_AA64MMFR2_ST_NONE (UL(0x0) << ID_AA64MMFR2_ST_SHIFT)
sys/arm64/include/armreg.h
1496
#define ID_AA64MMFR2_ST_IMPL (UL(0x1) << ID_AA64MMFR2_ST_SHIFT)
sys/arm64/include/armreg.h
1499
#define ID_AA64MMFR2_AT_MASK (UL(0xf) << ID_AA64MMFR2_AT_SHIFT)
sys/arm64/include/armreg.h
1501
#define ID_AA64MMFR2_AT_NONE (UL(0x0) << ID_AA64MMFR2_AT_SHIFT)
sys/arm64/include/armreg.h
1502
#define ID_AA64MMFR2_AT_IMPL (UL(0x1) << ID_AA64MMFR2_AT_SHIFT)
sys/arm64/include/armreg.h
1505
#define ID_AA64MMFR2_IDS_MASK (UL(0xf) << ID_AA64MMFR2_IDS_SHIFT)
sys/arm64/include/armreg.h
1507
#define ID_AA64MMFR2_IDS_NONE (UL(0x0) << ID_AA64MMFR2_IDS_SHIFT)
sys/arm64/include/armreg.h
1508
#define ID_AA64MMFR2_IDS_IMPL (UL(0x1) << ID_AA64MMFR2_IDS_SHIFT)
sys/arm64/include/armreg.h
1511
#define ID_AA64MMFR2_FWB_MASK (UL(0xf) << ID_AA64MMFR2_FWB_SHIFT)
sys/arm64/include/armreg.h
1513
#define ID_AA64MMFR2_FWB_NONE (UL(0x0) << ID_AA64MMFR2_FWB_SHIFT)
sys/arm64/include/armreg.h
1514
#define ID_AA64MMFR2_FWB_IMPL (UL(0x1) << ID_AA64MMFR2_FWB_SHIFT)
sys/arm64/include/armreg.h
1517
#define ID_AA64MMFR2_TTL_MASK (UL(0xf) << ID_AA64MMFR2_TTL_SHIFT)
sys/arm64/include/armreg.h
1519
#define ID_AA64MMFR2_TTL_NONE (UL(0x0) << ID_AA64MMFR2_TTL_SHIFT)
sys/arm64/include/armreg.h
1520
#define ID_AA64MMFR2_TTL_IMPL (UL(0x1) << ID_AA64MMFR2_TTL_SHIFT)
sys/arm64/include/armreg.h
1523
#define ID_AA64MMFR2_BBM_MASK (UL(0xf) << ID_AA64MMFR2_BBM_SHIFT)
sys/arm64/include/armreg.h
1525
#define ID_AA64MMFR2_BBM_LEVEL0 (UL(0x0) << ID_AA64MMFR2_BBM_SHIFT)
sys/arm64/include/armreg.h
1526
#define ID_AA64MMFR2_BBM_LEVEL1 (UL(0x1) << ID_AA64MMFR2_BBM_SHIFT)
sys/arm64/include/armreg.h
1527
#define ID_AA64MMFR2_BBM_LEVEL2 (UL(0x2) << ID_AA64MMFR2_BBM_SHIFT)
sys/arm64/include/armreg.h
1530
#define ID_AA64MMFR2_EVT_MASK (UL(0xf) << ID_AA64MMFR2_EVT_SHIFT)
sys/arm64/include/armreg.h
1532
#define ID_AA64MMFR2_EVT_NONE (UL(0x0) << ID_AA64MMFR2_EVT_SHIFT)
sys/arm64/include/armreg.h
1533
#define ID_AA64MMFR2_EVT_8_2 (UL(0x1) << ID_AA64MMFR2_EVT_SHIFT)
sys/arm64/include/armreg.h
1534
#define ID_AA64MMFR2_EVT_8_5 (UL(0x2) << ID_AA64MMFR2_EVT_SHIFT)
sys/arm64/include/armreg.h
1537
#define ID_AA64MMFR2_E0PD_MASK (UL(0xf) << ID_AA64MMFR2_E0PD_SHIFT)
sys/arm64/include/armreg.h
1539
#define ID_AA64MMFR2_E0PD_NONE (UL(0x0) << ID_AA64MMFR2_E0PD_SHIFT)
sys/arm64/include/armreg.h
1540
#define ID_AA64MMFR2_E0PD_IMPL (UL(0x1) << ID_AA64MMFR2_E0PD_SHIFT)
sys/arm64/include/armreg.h
1552
#define ID_AA64MMFR3_TCRX_MASK (UL(0xf) << ID_AA64MMFR3_TCRX_SHIFT)
sys/arm64/include/armreg.h
1554
#define ID_AA64MMFR3_TCRX_NONE (UL(0x0) << ID_AA64MMFR3_TCRX_SHIFT)
sys/arm64/include/armreg.h
1555
#define ID_AA64MMFR3_TCRX_IMPL (UL(0x1) << ID_AA64MMFR3_TCRX_SHIFT)
sys/arm64/include/armreg.h
1558
#define ID_AA64MMFR3_SCTLRX_MASK (UL(0xf) << ID_AA64MMFR3_SCTLRX_SHIFT)
sys/arm64/include/armreg.h
1560
#define ID_AA64MMFR3_SCTLRX_NONE (UL(0x0) << ID_AA64MMFR3_SCTLRX_SHIFT)
sys/arm64/include/armreg.h
1561
#define ID_AA64MMFR3_SCTLRX_IMPL (UL(0x1) << ID_AA64MMFR3_SCTLRX_SHIFT)
sys/arm64/include/armreg.h
1564
#define ID_AA64MMFR3_S1PIE_MASK (UL(0xf) << ID_AA64MMFR3_S1PIE_SHIFT)
sys/arm64/include/armreg.h
1566
#define ID_AA64MMFR3_S1PIE_NONE (UL(0x0) << ID_AA64MMFR3_S1PIE_SHIFT)
sys/arm64/include/armreg.h
1567
#define ID_AA64MMFR3_S1PIE_IMPL (UL(0x1) << ID_AA64MMFR3_S1PIE_SHIFT)
sys/arm64/include/armreg.h
1570
#define ID_AA64MMFR3_S2PIE_MASK (UL(0xf) << ID_AA64MMFR3_S2PIE_SHIFT)
sys/arm64/include/armreg.h
1572
#define ID_AA64MMFR3_S2PIE_NONE (UL(0x0) << ID_AA64MMFR3_S2PIE_SHIFT)
sys/arm64/include/armreg.h
1573
#define ID_AA64MMFR3_S2PIE_IMPL (UL(0x1) << ID_AA64MMFR3_S2PIE_SHIFT)
sys/arm64/include/armreg.h
1576
#define ID_AA64MMFR3_S1POE_MASK (UL(0xf) << ID_AA64MMFR3_S1POE_SHIFT)
sys/arm64/include/armreg.h
1578
#define ID_AA64MMFR3_S1POE_NONE (UL(0x0) << ID_AA64MMFR3_S1POE_SHIFT)
sys/arm64/include/armreg.h
1579
#define ID_AA64MMFR3_S1POE_IMPL (UL(0x1) << ID_AA64MMFR3_S1POE_SHIFT)
sys/arm64/include/armreg.h
1582
#define ID_AA64MMFR3_S2POE_MASK (UL(0xf) << ID_AA64MMFR3_S2POE_SHIFT)
sys/arm64/include/armreg.h
1584
#define ID_AA64MMFR3_S2POE_NONE (UL(0x0) << ID_AA64MMFR3_S2POE_SHIFT)
sys/arm64/include/armreg.h
1585
#define ID_AA64MMFR3_S2POE_IMPL (UL(0x1) << ID_AA64MMFR3_S2POE_SHIFT)
sys/arm64/include/armreg.h
1588
#define ID_AA64MMFR3_AIE_MASK (UL(0xf) << ID_AA64MMFR3_AIE_SHIFT)
sys/arm64/include/armreg.h
1590
#define ID_AA64MMFR3_AIE_NONE (UL(0x0) << ID_AA64MMFR3_AIE_SHIFT)
sys/arm64/include/armreg.h
1591
#define ID_AA64MMFR3_AIE_IMPL (UL(0x1) << ID_AA64MMFR3_AIE_SHIFT)
sys/arm64/include/armreg.h
1594
#define ID_AA64MMFR3_MEC_MASK (UL(0xf) << ID_AA64MMFR3_MEC_SHIFT)
sys/arm64/include/armreg.h
1596
#define ID_AA64MMFR3_MEC_NONE (UL(0x0) << ID_AA64MMFR3_MEC_SHIFT)
sys/arm64/include/armreg.h
1597
#define ID_AA64MMFR3_MEC_IMPL (UL(0x1) << ID_AA64MMFR3_MEC_SHIFT)
sys/arm64/include/armreg.h
1600
#define ID_AA64MMFR3_SNERR_MASK (UL(0xf) << ID_AA64MMFR3_SNERR_SHIFT)
sys/arm64/include/armreg.h
1602
#define ID_AA64MMFR3_SNERR_NONE (UL(0x0) << ID_AA64MMFR3_SNERR_SHIFT)
sys/arm64/include/armreg.h
1603
#define ID_AA64MMFR3_SNERR_ALL (UL(0x1) << ID_AA64MMFR3_SNERR_SHIFT)
sys/arm64/include/armreg.h
1606
#define ID_AA64MMFR3_ANERR_MASK (UL(0xf) << ID_AA64MMFR3_ANERR_SHIFT)
sys/arm64/include/armreg.h
1608
#define ID_AA64MMFR3_ANERR_NONE (UL(0x0) << ID_AA64MMFR3_ANERR_SHIFT)
sys/arm64/include/armreg.h
1609
#define ID_AA64MMFR3_ANERR_SOME (UL(0x1) << ID_AA64MMFR3_ANERR_SHIFT)
sys/arm64/include/armreg.h
1612
#define ID_AA64MMFR3_SDERR_MASK (UL(0xf) << ID_AA64MMFR3_SDERR_SHIFT)
sys/arm64/include/armreg.h
1614
#define ID_AA64MMFR3_SDERR_NONE (UL(0x0) << ID_AA64MMFR3_SDERR_SHIFT)
sys/arm64/include/armreg.h
1615
#define ID_AA64MMFR3_SDERR_ALL (UL(0x1) << ID_AA64MMFR3_SDERR_SHIFT)
sys/arm64/include/armreg.h
1618
#define ID_AA64MMFR3_ADERR_MASK (UL(0xf) << ID_AA64MMFR3_ADERR_SHIFT)
sys/arm64/include/armreg.h
1620
#define ID_AA64MMFR3_ADERR_NONE (UL(0x0) << ID_AA64MMFR3_ADERR_SHIFT)
sys/arm64/include/armreg.h
1621
#define ID_AA64MMFR3_ADERR_SOME (UL(0x1) << ID_AA64MMFR3_ADERR_SHIFT)
sys/arm64/include/armreg.h
1624
#define ID_AA64MMFR3_Spec_FPACC_MASK (UL(0xf) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
sys/arm64/include/armreg.h
1626
#define ID_AA64MMFR3_Spec_FPACC_NONE (UL(0x0) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
sys/arm64/include/armreg.h
1627
#define ID_AA64MMFR3_Spec_FPACC_IMPL (UL(0x1) << ID_AA64MMFR3_Spec_FPACC_SHIFT)
sys/arm64/include/armreg.h
1648
#define ID_AA64PFR0_EL0_MASK (UL(0xf) << ID_AA64PFR0_EL0_SHIFT)
sys/arm64/include/armreg.h
1650
#define ID_AA64PFR0_EL0_64 (UL(0x1) << ID_AA64PFR0_EL0_SHIFT)
sys/arm64/include/armreg.h
1651
#define ID_AA64PFR0_EL0_64_32 (UL(0x2) << ID_AA64PFR0_EL0_SHIFT)
sys/arm64/include/armreg.h
1654
#define ID_AA64PFR0_EL1_MASK (UL(0xf) << ID_AA64PFR0_EL1_SHIFT)
sys/arm64/include/armreg.h
1656
#define ID_AA64PFR0_EL1_64 (UL(0x1) << ID_AA64PFR0_EL1_SHIFT)
sys/arm64/include/armreg.h
1657
#define ID_AA64PFR0_EL1_64_32 (UL(0x2) << ID_AA64PFR0_EL1_SHIFT)
sys/arm64/include/armreg.h
1660
#define ID_AA64PFR0_EL2_MASK (UL(0xf) << ID_AA64PFR0_EL2_SHIFT)
sys/arm64/include/armreg.h
1662
#define ID_AA64PFR0_EL2_NONE (UL(0x0) << ID_AA64PFR0_EL2_SHIFT)
sys/arm64/include/armreg.h
1663
#define ID_AA64PFR0_EL2_64 (UL(0x1) << ID_AA64PFR0_EL2_SHIFT)
sys/arm64/include/armreg.h
1664
#define ID_AA64PFR0_EL2_64_32 (UL(0x2) << ID_AA64PFR0_EL2_SHIFT)
sys/arm64/include/armreg.h
1667
#define ID_AA64PFR0_EL3_MASK (UL(0xf) << ID_AA64PFR0_EL3_SHIFT)
sys/arm64/include/armreg.h
1669
#define ID_AA64PFR0_EL3_NONE (UL(0x0) << ID_AA64PFR0_EL3_SHIFT)
sys/arm64/include/armreg.h
1670
#define ID_AA64PFR0_EL3_64 (UL(0x1) << ID_AA64PFR0_EL3_SHIFT)
sys/arm64/include/armreg.h
1671
#define ID_AA64PFR0_EL3_64_32 (UL(0x2) << ID_AA64PFR0_EL3_SHIFT)
sys/arm64/include/armreg.h
1674
#define ID_AA64PFR0_FP_MASK (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
sys/arm64/include/armreg.h
1676
#define ID_AA64PFR0_FP_IMPL (UL(0x0) << ID_AA64PFR0_FP_SHIFT)
sys/arm64/include/armreg.h
1677
#define ID_AA64PFR0_FP_HP (UL(0x1) << ID_AA64PFR0_FP_SHIFT)
sys/arm64/include/armreg.h
1678
#define ID_AA64PFR0_FP_NONE (UL(0xf) << ID_AA64PFR0_FP_SHIFT)
sys/arm64/include/armreg.h
1681
#define ID_AA64PFR0_AdvSIMD_MASK (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
sys/arm64/include/armreg.h
1683
#define ID_AA64PFR0_AdvSIMD_IMPL (UL(0x0) << ID_AA64PFR0_AdvSIMD_SHIFT)
sys/arm64/include/armreg.h
1684
#define ID_AA64PFR0_AdvSIMD_HP (UL(0x1) << ID_AA64PFR0_AdvSIMD_SHIFT)
sys/arm64/include/armreg.h
1685
#define ID_AA64PFR0_AdvSIMD_NONE (UL(0xf) << ID_AA64PFR0_AdvSIMD_SHIFT)
sys/arm64/include/armreg.h
1689
#define ID_AA64PFR0_GIC_MASK (UL(0xf) << ID_AA64PFR0_GIC_SHIFT)
sys/arm64/include/armreg.h
1691
#define ID_AA64PFR0_GIC_CPUIF_NONE (UL(0x0) << ID_AA64PFR0_GIC_SHIFT)
sys/arm64/include/armreg.h
1692
#define ID_AA64PFR0_GIC_CPUIF_EN (UL(0x1) << ID_AA64PFR0_GIC_SHIFT)
sys/arm64/include/armreg.h
1693
#define ID_AA64PFR0_GIC_CPUIF_4_1 (UL(0x3) << ID_AA64PFR0_GIC_SHIFT)
sys/arm64/include/armreg.h
1696
#define ID_AA64PFR0_RAS_MASK (UL(0xf) << ID_AA64PFR0_RAS_SHIFT)
sys/arm64/include/armreg.h
1698
#define ID_AA64PFR0_RAS_NONE (UL(0x0) << ID_AA64PFR0_RAS_SHIFT)
sys/arm64/include/armreg.h
1699
#define ID_AA64PFR0_RAS_IMPL (UL(0x1) << ID_AA64PFR0_RAS_SHIFT)
sys/arm64/include/armreg.h
1700
#define ID_AA64PFR0_RAS_8_4 (UL(0x2) << ID_AA64PFR0_RAS_SHIFT)
sys/arm64/include/armreg.h
1701
#define ID_AA64PFR0_RAS_8_9 (UL(0x3) << ID_AA64PFR0_RAS_SHIFT)
sys/arm64/include/armreg.h
1704
#define ID_AA64PFR0_SVE_MASK (UL(0xf) << ID_AA64PFR0_SVE_SHIFT)
sys/arm64/include/armreg.h
1706
#define ID_AA64PFR0_SVE_NONE (UL(0x0) << ID_AA64PFR0_SVE_SHIFT)
sys/arm64/include/armreg.h
1707
#define ID_AA64PFR0_SVE_IMPL (UL(0x1) << ID_AA64PFR0_SVE_SHIFT)
sys/arm64/include/armreg.h
1710
#define ID_AA64PFR0_SEL2_MASK (UL(0xf) << ID_AA64PFR0_SEL2_SHIFT)
sys/arm64/include/armreg.h
1712
#define ID_AA64PFR0_SEL2_NONE (UL(0x0) << ID_AA64PFR0_SEL2_SHIFT)
sys/arm64/include/armreg.h
1713
#define ID_AA64PFR0_SEL2_IMPL (UL(0x1) << ID_AA64PFR0_SEL2_SHIFT)
sys/arm64/include/armreg.h
1716
#define ID_AA64PFR0_MPAM_MASK (UL(0xf) << ID_AA64PFR0_MPAM_SHIFT)
sys/arm64/include/armreg.h
1718
#define ID_AA64PFR0_MPAM_NONE (UL(0x0) << ID_AA64PFR0_MPAM_SHIFT)
sys/arm64/include/armreg.h
1719
#define ID_AA64PFR0_MPAM_IMPL (UL(0x1) << ID_AA64PFR0_MPAM_SHIFT)
sys/arm64/include/armreg.h
1722
#define ID_AA64PFR0_AMU_MASK (UL(0xf) << ID_AA64PFR0_AMU_SHIFT)
sys/arm64/include/armreg.h
1724
#define ID_AA64PFR0_AMU_NONE (UL(0x0) << ID_AA64PFR0_AMU_SHIFT)
sys/arm64/include/armreg.h
1725
#define ID_AA64PFR0_AMU_V1 (UL(0x1) << ID_AA64PFR0_AMU_SHIFT)
sys/arm64/include/armreg.h
1726
#define ID_AA64PFR0_AMU_V1_1 (UL(0x2) << ID_AA64PFR0_AMU_SHIFT)
sys/arm64/include/armreg.h
1729
#define ID_AA64PFR0_DIT_MASK (UL(0xf) << ID_AA64PFR0_DIT_SHIFT)
sys/arm64/include/armreg.h
1731
#define ID_AA64PFR0_DIT_NONE (UL(0x0) << ID_AA64PFR0_DIT_SHIFT)
sys/arm64/include/armreg.h
1732
#define ID_AA64PFR0_DIT_PSTATE (UL(0x1) << ID_AA64PFR0_DIT_SHIFT)
sys/arm64/include/armreg.h
1735
#define ID_AA64PFR0_RME_MASK (UL(0xf) << ID_AA64PFR0_RME_SHIFT)
sys/arm64/include/armreg.h
1737
#define ID_AA64PFR0_RME_NONE (UL(0x0) << ID_AA64PFR0_RME_SHIFT)
sys/arm64/include/armreg.h
1738
#define ID_AA64PFR0_RME_IMPL (UL(0x1) << ID_AA64PFR0_RME_SHIFT)
sys/arm64/include/armreg.h
1741
#define ID_AA64PFR0_CSV2_MASK (UL(0xf) << ID_AA64PFR0_CSV2_SHIFT)
sys/arm64/include/armreg.h
1743
#define ID_AA64PFR0_CSV2_NONE (UL(0x0) << ID_AA64PFR0_CSV2_SHIFT)
sys/arm64/include/armreg.h
1744
#define ID_AA64PFR0_CSV2_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV2_SHIFT)
sys/arm64/include/armreg.h
1745
#define ID_AA64PFR0_CSV2_SCXTNUM (UL(0x2) << ID_AA64PFR0_CSV2_SHIFT)
sys/arm64/include/armreg.h
1746
#define ID_AA64PFR0_CSV2_3 (UL(0x3) << ID_AA64PFR0_CSV2_SHIFT)
sys/arm64/include/armreg.h
1749
#define ID_AA64PFR0_CSV3_MASK (UL(0xf) << ID_AA64PFR0_CSV3_SHIFT)
sys/arm64/include/armreg.h
1751
#define ID_AA64PFR0_CSV3_NONE (UL(0x0) << ID_AA64PFR0_CSV3_SHIFT)
sys/arm64/include/armreg.h
1752
#define ID_AA64PFR0_CSV3_ISOLATED (UL(0x1) << ID_AA64PFR0_CSV3_SHIFT)
sys/arm64/include/armreg.h
1764
#define ID_AA64PFR1_BT_MASK (UL(0xf) << ID_AA64PFR1_BT_SHIFT)
sys/arm64/include/armreg.h
1766
#define ID_AA64PFR1_BT_NONE (UL(0x0) << ID_AA64PFR1_BT_SHIFT)
sys/arm64/include/armreg.h
1767
#define ID_AA64PFR1_BT_IMPL (UL(0x1) << ID_AA64PFR1_BT_SHIFT)
sys/arm64/include/armreg.h
1770
#define ID_AA64PFR1_SSBS_MASK (UL(0xf) << ID_AA64PFR1_SSBS_SHIFT)
sys/arm64/include/armreg.h
1772
#define ID_AA64PFR1_SSBS_NONE (UL(0x0) << ID_AA64PFR1_SSBS_SHIFT)
sys/arm64/include/armreg.h
1773
#define ID_AA64PFR1_SSBS_PSTATE (UL(0x1) << ID_AA64PFR1_SSBS_SHIFT)
sys/arm64/include/armreg.h
1774
#define ID_AA64PFR1_SSBS_PSTATE_MSR (UL(0x2) << ID_AA64PFR1_SSBS_SHIFT)
sys/arm64/include/armreg.h
1777
#define ID_AA64PFR1_MTE_MASK (UL(0xf) << ID_AA64PFR1_MTE_SHIFT)
sys/arm64/include/armreg.h
1779
#define ID_AA64PFR1_MTE_NONE (UL(0x0) << ID_AA64PFR1_MTE_SHIFT)
sys/arm64/include/armreg.h
1780
#define ID_AA64PFR1_MTE_MTE (UL(0x1) << ID_AA64PFR1_MTE_SHIFT)
sys/arm64/include/armreg.h
1781
#define ID_AA64PFR1_MTE_MTE2 (UL(0x2) << ID_AA64PFR1_MTE_SHIFT)
sys/arm64/include/armreg.h
1782
#define ID_AA64PFR1_MTE_MTE3 (UL(0x3) << ID_AA64PFR1_MTE_SHIFT)
sys/arm64/include/armreg.h
1785
#define ID_AA64PFR1_RAS_frac_MASK (UL(0xf) << ID_AA64PFR1_RAS_frac_SHIFT)
sys/arm64/include/armreg.h
1787
#define ID_AA64PFR1_RAS_frac_p0 (UL(0x0) << ID_AA64PFR1_RAS_frac_SHIFT)
sys/arm64/include/armreg.h
1788
#define ID_AA64PFR1_RAS_frac_p1 (UL(0x1) << ID_AA64PFR1_RAS_frac_SHIFT)
sys/arm64/include/armreg.h
1791
#define ID_AA64PFR1_MPAM_frac_MASK (UL(0xf) << ID_AA64PFR1_MPAM_frac_SHIFT)
sys/arm64/include/armreg.h
1793
#define ID_AA64PFR1_MPAM_frac_p0 (UL(0x0) << ID_AA64PFR1_MPAM_frac_SHIFT)
sys/arm64/include/armreg.h
1794
#define ID_AA64PFR1_MPAM_frac_p1 (UL(0x1) << ID_AA64PFR1_MPAM_frac_SHIFT)
sys/arm64/include/armreg.h
1797
#define ID_AA64PFR1_SME_MASK (UL(0xf) << ID_AA64PFR1_SME_SHIFT)
sys/arm64/include/armreg.h
1799
#define ID_AA64PFR1_SME_NONE (UL(0x0) << ID_AA64PFR1_SME_SHIFT)
sys/arm64/include/armreg.h
1800
#define ID_AA64PFR1_SME_SME (UL(0x1) << ID_AA64PFR1_SME_SHIFT)
sys/arm64/include/armreg.h
1801
#define ID_AA64PFR1_SME_SME2 (UL(0x2) << ID_AA64PFR1_SME_SHIFT)
sys/arm64/include/armreg.h
1804
#define ID_AA64PFR1_RNDR_trap_MASK (UL(0xf) << ID_AA64PFR1_RNDR_trap_SHIFT)
sys/arm64/include/armreg.h
1806
#define ID_AA64PFR1_RNDR_trap_NONE (UL(0x0) << ID_AA64PFR1_RNDR_trap_SHIFT)
sys/arm64/include/armreg.h
1807
#define ID_AA64PFR1_RNDR_trap_IMPL (UL(0x1) << ID_AA64PFR1_RNDR_trap_SHIFT)
sys/arm64/include/armreg.h
1810
#define ID_AA64PFR1_CSV2_frac_MASK (UL(0xf) << ID_AA64PFR1_CSV2_frac_SHIFT)
sys/arm64/include/armreg.h
1812
#define ID_AA64PFR1_CSV2_frac_p0 (UL(0x0) << ID_AA64PFR1_CSV2_frac_SHIFT)
sys/arm64/include/armreg.h
1813
#define ID_AA64PFR1_CSV2_frac_p1 (UL(0x1) << ID_AA64PFR1_CSV2_frac_SHIFT)
sys/arm64/include/armreg.h
1814
#define ID_AA64PFR1_CSV2_frac_p2 (UL(0x2) << ID_AA64PFR1_CSV2_frac_SHIFT)
sys/arm64/include/armreg.h
1817
#define ID_AA64PFR1_NMI_MASK (UL(0xf) << ID_AA64PFR1_NMI_SHIFT)
sys/arm64/include/armreg.h
1819
#define ID_AA64PFR1_NMI_NONE (UL(0x0) << ID_AA64PFR1_NMI_SHIFT)
sys/arm64/include/armreg.h
1820
#define ID_AA64PFR1_NMI_IMPL (UL(0x1) << ID_AA64PFR1_NMI_SHIFT)
sys/arm64/include/armreg.h
1823
#define ID_AA64PFR1_MTE_frac_MASK (UL(0xf) << ID_AA64PFR1_MTE_frac_SHIFT)
sys/arm64/include/armreg.h
1825
#define ID_AA64PFR1_MTE_frac_IMPL (UL(0x0) << ID_AA64PFR1_MTE_frac_SHIFT)
sys/arm64/include/armreg.h
1826
#define ID_AA64PFR1_MTE_frac_NONE (UL(0xf) << ID_AA64PFR1_MTE_frac_SHIFT)
sys/arm64/include/armreg.h
1829
#define ID_AA64PFR1_THE_MASK (UL(0xf) << ID_AA64PFR1_THE_SHIFT)
sys/arm64/include/armreg.h
1831
#define ID_AA64PFR1_THE_NONE (UL(0x0) << ID_AA64PFR1_THE_SHIFT)
sys/arm64/include/armreg.h
1832
#define ID_AA64PFR1_THE_IMPL (UL(0x1) << ID_AA64PFR1_THE_SHIFT)
sys/arm64/include/armreg.h
1835
#define ID_AA64PFR1_MTEX_MASK (UL(0xf) << ID_AA64PFR1_MTEX_SHIFT)
sys/arm64/include/armreg.h
1837
#define ID_AA64PFR1_MTEX_NONE (UL(0x0) << ID_AA64PFR1_MTEX_SHIFT)
sys/arm64/include/armreg.h
1838
#define ID_AA64PFR1_MTEX_IMPL (UL(0x1) << ID_AA64PFR1_MTEX_SHIFT)
sys/arm64/include/armreg.h
1841
#define ID_AA64PFR1_DF2_MASK (UL(0xf) << ID_AA64PFR1_DF2_SHIFT)
sys/arm64/include/armreg.h
1843
#define ID_AA64PFR1_DF2_NONE (UL(0x0) << ID_AA64PFR1_DF2_SHIFT)
sys/arm64/include/armreg.h
1844
#define ID_AA64PFR1_DF2_IMPL (UL(0x1) << ID_AA64PFR1_DF2_SHIFT)
sys/arm64/include/armreg.h
1847
#define ID_AA64PFR1_PFAR_MASK (UL(0xf) << ID_AA64PFR1_PFAR_SHIFT)
sys/arm64/include/armreg.h
1849
#define ID_AA64PFR1_PFAR_NONE (UL(0x0) << ID_AA64PFR1_PFAR_SHIFT)
sys/arm64/include/armreg.h
1850
#define ID_AA64PFR1_PFAR_IMPL (UL(0x1) << ID_AA64PFR1_PFAR_SHIFT)
sys/arm64/include/armreg.h
1871
#define ID_AA64ZFR0_SVEver_MASK (UL(0xf) << ID_AA64ZFR0_SVEver_SHIFT)
sys/arm64/include/armreg.h
1873
#define ID_AA64ZFR0_SVEver_SVE1 (UL(0x0) << ID_AA64ZFR0_SVEver_SHIFT)
sys/arm64/include/armreg.h
1874
#define ID_AA64ZFR0_SVEver_SVE2 (UL(0x1) << ID_AA64ZFR0_SVEver_SHIFT)
sys/arm64/include/armreg.h
1875
#define ID_AA64ZFR0_SVEver_SVE2P1 (UL(0x2) << ID_AA64ZFR0_SVEver_SHIFT)
sys/arm64/include/armreg.h
1878
#define ID_AA64ZFR0_AES_MASK (UL(0xf) << ID_AA64ZFR0_AES_SHIFT)
sys/arm64/include/armreg.h
1880
#define ID_AA64ZFR0_AES_NONE (UL(0x0) << ID_AA64ZFR0_AES_SHIFT)
sys/arm64/include/armreg.h
1881
#define ID_AA64ZFR0_AES_BASE (UL(0x1) << ID_AA64ZFR0_AES_SHIFT)
sys/arm64/include/armreg.h
1882
#define ID_AA64ZFR0_AES_PMULL (UL(0x2) << ID_AA64ZFR0_AES_SHIFT)
sys/arm64/include/armreg.h
1885
#define ID_AA64ZFR0_BitPerm_MASK (UL(0xf) << ID_AA64ZFR0_BitPerm_SHIFT)
sys/arm64/include/armreg.h
1887
#define ID_AA64ZFR0_BitPerm_NONE (UL(0x0) << ID_AA64ZFR0_BitPerm_SHIFT)
sys/arm64/include/armreg.h
1888
#define ID_AA64ZFR0_BitPerm_IMPL (UL(0x1) << ID_AA64ZFR0_BitPerm_SHIFT)
sys/arm64/include/armreg.h
1891
#define ID_AA64ZFR0_BF16_MASK (UL(0xf) << ID_AA64ZFR0_BF16_SHIFT)
sys/arm64/include/armreg.h
1893
#define ID_AA64ZFR0_BF16_NONE (UL(0x0) << ID_AA64ZFR0_BF16_SHIFT)
sys/arm64/include/armreg.h
1894
#define ID_AA64ZFR0_BF16_BASE (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
sys/arm64/include/armreg.h
1895
#define ID_AA64ZFR0_BF16_EBF (UL(0x1) << ID_AA64ZFR0_BF16_SHIFT)
sys/arm64/include/armreg.h
1898
#define ID_AA64ZFR0_SHA3_MASK (UL(0xf) << ID_AA64ZFR0_SHA3_SHIFT)
sys/arm64/include/armreg.h
1900
#define ID_AA64ZFR0_SHA3_NONE (UL(0x0) << ID_AA64ZFR0_SHA3_SHIFT)
sys/arm64/include/armreg.h
1901
#define ID_AA64ZFR0_SHA3_IMPL (UL(0x1) << ID_AA64ZFR0_SHA3_SHIFT)
sys/arm64/include/armreg.h
1904
#define ID_AA64ZFR0_SM4_MASK (UL(0xf) << ID_AA64ZFR0_SM4_SHIFT)
sys/arm64/include/armreg.h
1906
#define ID_AA64ZFR0_SM4_NONE (UL(0x0) << ID_AA64ZFR0_SM4_SHIFT)
sys/arm64/include/armreg.h
1907
#define ID_AA64ZFR0_SM4_IMPL (UL(0x1) << ID_AA64ZFR0_SM4_SHIFT)
sys/arm64/include/armreg.h
1910
#define ID_AA64ZFR0_I8MM_MASK (UL(0xf) << ID_AA64ZFR0_I8MM_SHIFT)
sys/arm64/include/armreg.h
1912
#define ID_AA64ZFR0_I8MM_NONE (UL(0x0) << ID_AA64ZFR0_I8MM_SHIFT)
sys/arm64/include/armreg.h
1913
#define ID_AA64ZFR0_I8MM_IMPL (UL(0x1) << ID_AA64ZFR0_I8MM_SHIFT)
sys/arm64/include/armreg.h
1916
#define ID_AA64ZFR0_F32MM_MASK (UL(0xf) << ID_AA64ZFR0_F32MM_SHIFT)
sys/arm64/include/armreg.h
1918
#define ID_AA64ZFR0_F32MM_NONE (UL(0x0) << ID_AA64ZFR0_F32MM_SHIFT)
sys/arm64/include/armreg.h
1919
#define ID_AA64ZFR0_F32MM_IMPL (UL(0x1) << ID_AA64ZFR0_F32MM_SHIFT)
sys/arm64/include/armreg.h
1922
#define ID_AA64ZFR0_F64MM_MASK (UL(0xf) << ID_AA64ZFR0_F64MM_SHIFT)
sys/arm64/include/armreg.h
1924
#define ID_AA64ZFR0_F64MM_NONE (UL(0x0) << ID_AA64ZFR0_F64MM_SHIFT)
sys/arm64/include/armreg.h
1925
#define ID_AA64ZFR0_F64MM_IMPL (UL(0x1) << ID_AA64ZFR0_F64MM_SHIFT)
sys/arm64/include/armreg.h
1936
#define ID_ISAR5_SEVL_MASK (UL(0xf) << ID_ISAR5_SEVL_SHIFT)
sys/arm64/include/armreg.h
1938
#define ID_ISAR5_SEVL_NOP (UL(0x0) << ID_ISAR5_SEVL_SHIFT)
sys/arm64/include/armreg.h
1939
#define ID_ISAR5_SEVL_IMPL (UL(0x1) << ID_ISAR5_SEVL_SHIFT)
sys/arm64/include/armreg.h
1942
#define ID_ISAR5_AES_MASK (UL(0xf) << ID_ISAR5_AES_SHIFT)
sys/arm64/include/armreg.h
1944
#define ID_ISAR5_AES_NONE (UL(0x0) << ID_ISAR5_AES_SHIFT)
sys/arm64/include/armreg.h
1945
#define ID_ISAR5_AES_BASE (UL(0x1) << ID_ISAR5_AES_SHIFT)
sys/arm64/include/armreg.h
1946
#define ID_ISAR5_AES_VMULL (UL(0x2) << ID_ISAR5_AES_SHIFT)
sys/arm64/include/armreg.h
1949
#define ID_ISAR5_SHA1_MASK (UL(0xf) << ID_ISAR5_SHA1_SHIFT)
sys/arm64/include/armreg.h
1951
#define ID_ISAR5_SHA1_NONE (UL(0x0) << ID_ISAR5_SHA1_SHIFT)
sys/arm64/include/armreg.h
1952
#define ID_ISAR5_SHA1_IMPL (UL(0x1) << ID_ISAR5_SHA1_SHIFT)
sys/arm64/include/armreg.h
1955
#define ID_ISAR5_SHA2_MASK (UL(0xf) << ID_ISAR5_SHA2_SHIFT)
sys/arm64/include/armreg.h
1957
#define ID_ISAR5_SHA2_NONE (UL(0x0) << ID_ISAR5_SHA2_SHIFT)
sys/arm64/include/armreg.h
1958
#define ID_ISAR5_SHA2_IMPL (UL(0x1) << ID_ISAR5_SHA2_SHIFT)
sys/arm64/include/armreg.h
1961
#define ID_ISAR5_CRC32_MASK (UL(0xf) << ID_ISAR5_CRC32_SHIFT)
sys/arm64/include/armreg.h
1963
#define ID_ISAR5_CRC32_NONE (UL(0x0) << ID_ISAR5_CRC32_SHIFT)
sys/arm64/include/armreg.h
1964
#define ID_ISAR5_CRC32_IMPL (UL(0x1) << ID_ISAR5_CRC32_SHIFT)
sys/arm64/include/armreg.h
1967
#define ID_ISAR5_RDM_MASK (UL(0xf) << ID_ISAR5_RDM_SHIFT)
sys/arm64/include/armreg.h
1969
#define ID_ISAR5_RDM_NONE (UL(0x0) << ID_ISAR5_RDM_SHIFT)
sys/arm64/include/armreg.h
1970
#define ID_ISAR5_RDM_IMPL (UL(0x1) << ID_ISAR5_RDM_SHIFT)
sys/arm64/include/armreg.h
1973
#define ID_ISAR5_VCMA_MASK (UL(0xf) << ID_ISAR5_VCMA_SHIFT)
sys/arm64/include/armreg.h
1975
#define ID_ISAR5_VCMA_NONE (UL(0x0) << ID_ISAR5_VCMA_SHIFT)
sys/arm64/include/armreg.h
1976
#define ID_ISAR5_VCMA_IMPL (UL(0x1) << ID_ISAR5_VCMA_SHIFT)
sys/arm64/include/armreg.h
1985
#define MAIR_ATTR_MASK(idx) (UL(0xff) << ((idx) * 8))
sys/arm64/include/armreg.h
1987
#define MAIR_DEVICE_nGnRnE UL(0x00)
sys/arm64/include/armreg.h
1988
#define MAIR_DEVICE_nGnRE UL(0x04)
sys/arm64/include/armreg.h
1989
#define MAIR_NORMAL_NC UL(0x44)
sys/arm64/include/armreg.h
1990
#define MAIR_NORMAL_WT UL(0xbb)
sys/arm64/include/armreg.h
1991
#define MAIR_NORMAL_WB UL(0xff)
sys/arm64/include/armreg.h
2022
#define MDSCR_SS (UL(0x1) << MDSCR_SS_SHIFT)
sys/arm64/include/armreg.h
2024
#define MDSCR_KDE (UL(0x1) << MDSCR_KDE_SHIFT)
sys/arm64/include/armreg.h
2026
#define MDSCR_MDE (UL(0x1) << MDSCR_MDE_SHIFT)
sys/arm64/include/armreg.h
2042
#define MPIDR_AFF0_MASK (UL(0xff) << MPIDR_AFF0_SHIFT)
sys/arm64/include/armreg.h
2045
#define MPIDR_AFF1_MASK (UL(0xff) << MPIDR_AFF1_SHIFT)
sys/arm64/include/armreg.h
2048
#define MPIDR_AFF2_MASK (UL(0xff) << MPIDR_AFF2_SHIFT)
sys/arm64/include/armreg.h
2051
#define MPIDR_MT_MASK (UL(0x1) << MPIDR_MT_SHIFT)
sys/arm64/include/armreg.h
2053
#define MPIDR_U_MASK (UL(0x1) << MPIDR_U_SHIFT)
sys/arm64/include/armreg.h
2055
#define MPIDR_AFF3_MASK (UL(0xff) << MPIDR_AFF3_SHIFT)
sys/arm64/include/armreg.h
2067
#define MVFR0_SIMDReg_MASK (UL(0xf) << MVFR0_SIMDReg_SHIFT)
sys/arm64/include/armreg.h
2069
#define MVFR0_SIMDReg_NONE (UL(0x0) << MVFR0_SIMDReg_SHIFT)
sys/arm64/include/armreg.h
2070
#define MVFR0_SIMDReg_FP (UL(0x1) << MVFR0_SIMDReg_SHIFT)
sys/arm64/include/armreg.h
2071
#define MVFR0_SIMDReg_AdvSIMD (UL(0x2) << MVFR0_SIMDReg_SHIFT)
sys/arm64/include/armreg.h
2074
#define MVFR0_FPSP_MASK (UL(0xf) << MVFR0_FPSP_SHIFT)
sys/arm64/include/armreg.h
2076
#define MVFR0_FPSP_NONE (UL(0x0) << MVFR0_FPSP_SHIFT)
sys/arm64/include/armreg.h
2077
#define MVFR0_FPSP_VFP_v2 (UL(0x1) << MVFR0_FPSP_SHIFT)
sys/arm64/include/armreg.h
2078
#define MVFR0_FPSP_VFP_v3_v4 (UL(0x2) << MVFR0_FPSP_SHIFT)
sys/arm64/include/armreg.h
2081
#define MVFR0_FPDP_MASK (UL(0xf) << MVFR0_FPDP_SHIFT)
sys/arm64/include/armreg.h
2083
#define MVFR0_FPDP_NONE (UL(0x0) << MVFR0_FPDP_SHIFT)
sys/arm64/include/armreg.h
2084
#define MVFR0_FPDP_VFP_v2 (UL(0x1) << MVFR0_FPDP_SHIFT)
sys/arm64/include/armreg.h
2085
#define MVFR0_FPDP_VFP_v3_v4 (UL(0x2) << MVFR0_FPDP_SHIFT)
sys/arm64/include/armreg.h
2088
#define MVFR0_FPTrap_MASK (UL(0xf) << MVFR0_FPTrap_SHIFT)
sys/arm64/include/armreg.h
2090
#define MVFR0_FPTrap_NONE (UL(0x0) << MVFR0_FPTrap_SHIFT)
sys/arm64/include/armreg.h
2091
#define MVFR0_FPTrap_IMPL (UL(0x1) << MVFR0_FPTrap_SHIFT)
sys/arm64/include/armreg.h
2094
#define MVFR0_FPDivide_MASK (UL(0xf) << MVFR0_FPDivide_SHIFT)
sys/arm64/include/armreg.h
2096
#define MVFR0_FPDivide_NONE (UL(0x0) << MVFR0_FPDivide_SHIFT)
sys/arm64/include/armreg.h
2097
#define MVFR0_FPDivide_IMPL (UL(0x1) << MVFR0_FPDivide_SHIFT)
sys/arm64/include/armreg.h
2100
#define MVFR0_FPSqrt_MASK (UL(0xf) << MVFR0_FPSqrt_SHIFT)
sys/arm64/include/armreg.h
2102
#define MVFR0_FPSqrt_NONE (UL(0x0) << MVFR0_FPSqrt_SHIFT)
sys/arm64/include/armreg.h
2103
#define MVFR0_FPSqrt_IMPL (UL(0x1) << MVFR0_FPSqrt_SHIFT)
sys/arm64/include/armreg.h
2106
#define MVFR0_FPShVec_MASK (UL(0xf) << MVFR0_FPShVec_SHIFT)
sys/arm64/include/armreg.h
2108
#define MVFR0_FPShVec_NONE (UL(0x0) << MVFR0_FPShVec_SHIFT)
sys/arm64/include/armreg.h
2109
#define MVFR0_FPShVec_IMPL (UL(0x1) << MVFR0_FPShVec_SHIFT)
sys/arm64/include/armreg.h
2112
#define MVFR0_FPRound_MASK (UL(0xf) << MVFR0_FPRound_SHIFT)
sys/arm64/include/armreg.h
2114
#define MVFR0_FPRound_NONE (UL(0x0) << MVFR0_FPRound_SHIFT)
sys/arm64/include/armreg.h
2115
#define MVFR0_FPRound_IMPL (UL(0x1) << MVFR0_FPRound_SHIFT)
sys/arm64/include/armreg.h
2126
#define MVFR1_FPFtZ_MASK (UL(0xf) << MVFR1_FPFtZ_SHIFT)
sys/arm64/include/armreg.h
2128
#define MVFR1_FPFtZ_NONE (UL(0x0) << MVFR1_FPFtZ_SHIFT)
sys/arm64/include/armreg.h
2129
#define MVFR1_FPFtZ_IMPL (UL(0x1) << MVFR1_FPFtZ_SHIFT)
sys/arm64/include/armreg.h
2132
#define MVFR1_FPDNaN_MASK (UL(0xf) << MVFR1_FPDNaN_SHIFT)
sys/arm64/include/armreg.h
2134
#define MVFR1_FPDNaN_NONE (UL(0x0) << MVFR1_FPDNaN_SHIFT)
sys/arm64/include/armreg.h
2135
#define MVFR1_FPDNaN_IMPL (UL(0x1) << MVFR1_FPDNaN_SHIFT)
sys/arm64/include/armreg.h
2138
#define MVFR1_SIMDLS_MASK (UL(0xf) << MVFR1_SIMDLS_SHIFT)
sys/arm64/include/armreg.h
2140
#define MVFR1_SIMDLS_NONE (UL(0x0) << MVFR1_SIMDLS_SHIFT)
sys/arm64/include/armreg.h
2141
#define MVFR1_SIMDLS_IMPL (UL(0x1) << MVFR1_SIMDLS_SHIFT)
sys/arm64/include/armreg.h
2144
#define MVFR1_SIMDInt_MASK (UL(0xf) << MVFR1_SIMDInt_SHIFT)
sys/arm64/include/armreg.h
2146
#define MVFR1_SIMDInt_NONE (UL(0x0) << MVFR1_SIMDInt_SHIFT)
sys/arm64/include/armreg.h
2147
#define MVFR1_SIMDInt_IMPL (UL(0x1) << MVFR1_SIMDInt_SHIFT)
sys/arm64/include/armreg.h
2150
#define MVFR1_SIMDSP_MASK (UL(0xf) << MVFR1_SIMDSP_SHIFT)
sys/arm64/include/armreg.h
2152
#define MVFR1_SIMDSP_NONE (UL(0x0) << MVFR1_SIMDSP_SHIFT)
sys/arm64/include/armreg.h
2153
#define MVFR1_SIMDSP_IMPL (UL(0x1) << MVFR1_SIMDSP_SHIFT)
sys/arm64/include/armreg.h
2156
#define MVFR1_SIMDHP_MASK (UL(0xf) << MVFR1_SIMDHP_SHIFT)
sys/arm64/include/armreg.h
2158
#define MVFR1_SIMDHP_NONE (UL(0x0) << MVFR1_SIMDHP_SHIFT)
sys/arm64/include/armreg.h
2159
#define MVFR1_SIMDHP_CONV_SP (UL(0x1) << MVFR1_SIMDHP_SHIFT)
sys/arm64/include/armreg.h
2160
#define MVFR1_SIMDHP_ARITH (UL(0x2) << MVFR1_SIMDHP_SHIFT)
sys/arm64/include/armreg.h
2163
#define MVFR1_FPHP_MASK (UL(0xf) << MVFR1_FPHP_SHIFT)
sys/arm64/include/armreg.h
2165
#define MVFR1_FPHP_NONE (UL(0x0) << MVFR1_FPHP_SHIFT)
sys/arm64/include/armreg.h
2166
#define MVFR1_FPHP_CONV_SP (UL(0x1) << MVFR1_FPHP_SHIFT)
sys/arm64/include/armreg.h
2167
#define MVFR1_FPHP_CONV_DP (UL(0x2) << MVFR1_FPHP_SHIFT)
sys/arm64/include/armreg.h
2168
#define MVFR1_FPHP_ARITH (UL(0x3) << MVFR1_FPHP_SHIFT)
sys/arm64/include/armreg.h
2171
#define MVFR1_SIMDFMAC_MASK (UL(0xf) << MVFR1_SIMDFMAC_SHIFT)
sys/arm64/include/armreg.h
2173
#define MVFR1_SIMDFMAC_NONE (UL(0x0) << MVFR1_SIMDFMAC_SHIFT)
sys/arm64/include/armreg.h
2174
#define MVFR1_SIMDFMAC_IMPL (UL(0x1) << MVFR1_SIMDFMAC_SHIFT)
sys/arm64/include/armreg.h
2232
#define PMBIDR_Align_MASK (UL(0xf) << PMBIDR_Align_SHIFT)
sys/arm64/include/armreg.h
2234
#define PMBIDR_P (UL(0x1) << PMBIDR_P_SHIFT)
sys/arm64/include/armreg.h
2236
#define PMBIDR_F (UL(0x1) << PMBIDR_F_SHIFT)
sys/arm64/include/armreg.h
2246
#define PMBLIMITR_E (UL(0x1) << PMBLIMITR_E_SHIFT)
sys/arm64/include/armreg.h
2248
#define PMBLIMITR_FM_MASK (UL(0x3) << PMBLIMITR_FM_SHIFT)
sys/arm64/include/armreg.h
2250
#define PMBLIMITR_PMFZ (UL(0x1) << PMBLIMITR_PMFZ_SHIFT)
sys/arm64/include/armreg.h
2253
(UL(0xfffffffffffff) << PMBLIMITR_LIMIT_SHIFT)
sys/arm64/include/armreg.h
2264
(UL(0xffffffffffffffff) << PMBPTR_PTR_SHIFT)
sys/arm64/include/armreg.h
2274
#define PMBSR_MSS_MASK (UL(0xffff) << PMBSR_MSS_SHIFT)
sys/arm64/include/armreg.h
2275
#define PMBSR_MSS_BSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT)
sys/arm64/include/armreg.h
2276
#define PMBSR_MSS_BSC_BUFFER_FILLED (UL(0x01) << PMBSR_MSS_SHIFT)
sys/arm64/include/armreg.h
2277
#define PMBSR_MSS_FSC_MASK (UL(0x3f) << PMBSR_MSS_SHIFT)
sys/arm64/include/armreg.h
2279
#define PMBSR_COLL (UL(0x1) << PMBSR_COLL_SHIFT)
sys/arm64/include/armreg.h
2281
#define PMBSR_S (UL(0x1) << PMBSR_S_SHIFT)
sys/arm64/include/armreg.h
2283
#define PMBSR_EA (UL(0x1) << PMBSR_EA_SHIFT)
sys/arm64/include/armreg.h
2285
#define PMBSR_DL (UL(0x1) << PMBSR_DL_SHIFT)
sys/arm64/include/armreg.h
2287
#define PMBSR_EC_MASK (UL(0x3f) << PMBSR_EC_SHIFT)
sys/arm64/include/armreg.h
2443
#define PMSCR_E0SPE (UL(0x1) << PMSCR_E0SPE_SHIFT)
sys/arm64/include/armreg.h
2445
#define PMSCR_E1SPE (UL(0x1) << PMSCR_E1SPE_SHIFT)
sys/arm64/include/armreg.h
2447
#define PMSCR_CX (UL(0x1) << PMSCR_CX_SHIFT)
sys/arm64/include/armreg.h
2449
#define PMSCR_PA (UL(0x1) << PMSCR_PA_SHIFT)
sys/arm64/include/armreg.h
2451
#define PMSCR_TS (UL(0x1) << PMSCR_TS_SHIFT)
sys/arm64/include/armreg.h
2453
#define PMSCR_PCT_MASK (UL(0x3) << PMSCR_PCT_SHIFT)
sys/arm64/include/armreg.h
2479
#define PMSFCR_FE (UL(0x1) << PMSFCR_FE_SHIFT)
sys/arm64/include/armreg.h
2481
#define PMSFCR_FT (UL(0x1) << PMSFCR_FT_SHIFT)
sys/arm64/include/armreg.h
2483
#define PMSFCR_FL (UL(0x1) << PMSFCR_FL_SHIFT)
sys/arm64/include/armreg.h
2485
#define PMSFCR_FnE (UL(0x1) << PMSFCR_FnE_SHIFT)
sys/arm64/include/armreg.h
2487
#define PMSFCR_B (UL(0x1) << PMSFCR_B_SHIFT)
sys/arm64/include/armreg.h
2489
#define PMSFCR_LD (UL(0x1) << PMSFCR_LD_SHIFT)
sys/arm64/include/armreg.h
2491
#define PMSFCR_ST (UL(0x1) << PMSFCR_ST_SHIFT)
sys/arm64/include/armreg.h
2501
#define PMSICR_COUNT_MASK (UL(0xffffffff) << PMSICR_COUNT_SHIFT)
sys/arm64/include/armreg.h
2503
#define PMSICR_ECOUNT_MASK (UL(0xff) << PMSICR_ECOUNT_SHIFT)
sys/arm64/include/armreg.h
2513
#define PMSIDR_FE (UL(0x1) << PMSIDR_FE_SHIFT)
sys/arm64/include/armreg.h
2515
#define PMSIDR_FT (UL(0x1) << PMSIDR_FT_SHIFT)
sys/arm64/include/armreg.h
2517
#define PMSIDR_FL (UL(0x1) << PMSIDR_FL_SHIFT)
sys/arm64/include/armreg.h
2519
#define PMSIDR_ArchInst (UL(0x1) << PMSIDR_ArchInst_SHIFT)
sys/arm64/include/armreg.h
2521
#define PMSIDR_LDS (UL(0x1) << PMSIDR_LDS_SHIFT)
sys/arm64/include/armreg.h
2523
#define PMSIDR_ERnd (UL(0x1) << PMSIDR_ERnd_SHIFT)
sys/arm64/include/armreg.h
2525
#define PMSIDR_FnE (UL(0x1) << PMSIDR_FnE_SHIFT)
sys/arm64/include/armreg.h
2527
#define PMSIDR_Interval_MASK (UL(0xf) << PMSIDR_Interval_SHIFT)
sys/arm64/include/armreg.h
2538
#define PMSIDR_MaxSize_MASK (UL(0xf) << PMSIDR_MaxSize_SHIFT)
sys/arm64/include/armreg.h
2540
#define PMSIDR_CountSize_MASK (UL(0xf) << PMSIDR_CountSize_SHIFT)
sys/arm64/include/armreg.h
2542
#define PMSIDR_Format_MASK (UL(0xf) << PMSIDR_Format_SHIFT)
sys/arm64/include/armreg.h
2544
#define PMSIDR_PBT (UL(0x1) << PMSIDR_PBT_SHIFT)
sys/arm64/include/armreg.h
2554
#define PMSIRR_RND (UL(0x1) << PMSIRR_RND_SHIFT)
sys/arm64/include/armreg.h
2556
#define PMSIRR_INTERVAL_MASK (UL(0xffffff) << PMSIRR_INTERVAL_SHIFT)
sys/arm64/include/armreg.h
2566
#define PMSLATFR_MINLAT_MASK (UL(0xfff) << PMSLATFR_MINLAT_SHIFT)
sys/arm64/include/armreg.h
2620
#define SCTLR_M (UL(0x1) << 0)
sys/arm64/include/armreg.h
2621
#define SCTLR_A (UL(0x1) << 1)
sys/arm64/include/armreg.h
2622
#define SCTLR_C (UL(0x1) << 2)
sys/arm64/include/armreg.h
2623
#define SCTLR_SA (UL(0x1) << 3)
sys/arm64/include/armreg.h
2624
#define SCTLR_SA0 (UL(0x1) << 4)
sys/arm64/include/armreg.h
2625
#define SCTLR_CP15BEN (UL(0x1) << 5)
sys/arm64/include/armreg.h
2626
#define SCTLR_nAA (UL(0x1) << 6)
sys/arm64/include/armreg.h
2627
#define SCTLR_ITD (UL(0x1) << 7)
sys/arm64/include/armreg.h
2628
#define SCTLR_SED (UL(0x1) << 8)
sys/arm64/include/armreg.h
2629
#define SCTLR_UMA (UL(0x1) << 9)
sys/arm64/include/armreg.h
2630
#define SCTLR_EnRCTX (UL(0x1) << 10)
sys/arm64/include/armreg.h
2631
#define SCTLR_EOS (UL(0x1) << 11)
sys/arm64/include/armreg.h
2632
#define SCTLR_I (UL(0x1) << 12)
sys/arm64/include/armreg.h
2633
#define SCTLR_EnDB (UL(0x1) << 13)
sys/arm64/include/armreg.h
2634
#define SCTLR_DZE (UL(0x1) << 14)
sys/arm64/include/armreg.h
2635
#define SCTLR_UCT (UL(0x1) << 15)
sys/arm64/include/armreg.h
2636
#define SCTLR_nTWI (UL(0x1) << 16)
sys/arm64/include/armreg.h
2638
#define SCTLR_nTWE (UL(0x1) << 18)
sys/arm64/include/armreg.h
2639
#define SCTLR_WXN (UL(0x1) << 19)
sys/arm64/include/armreg.h
2640
#define SCTLR_TSCXT (UL(0x1) << 20)
sys/arm64/include/armreg.h
2641
#define SCTLR_IESB (UL(0x1) << 21)
sys/arm64/include/armreg.h
2642
#define SCTLR_EIS (UL(0x1) << 22)
sys/arm64/include/armreg.h
2643
#define SCTLR_SPAN (UL(0x1) << 23)
sys/arm64/include/armreg.h
2644
#define SCTLR_E0E (UL(0x1) << 24)
sys/arm64/include/armreg.h
2645
#define SCTLR_EE (UL(0x1) << 25)
sys/arm64/include/armreg.h
2646
#define SCTLR_UCI (UL(0x1) << 26)
sys/arm64/include/armreg.h
2647
#define SCTLR_EnDA (UL(0x1) << 27)
sys/arm64/include/armreg.h
2648
#define SCTLR_nTLSMD (UL(0x1) << 28)
sys/arm64/include/armreg.h
2649
#define SCTLR_LSMAOE (UL(0x1) << 29)
sys/arm64/include/armreg.h
2650
#define SCTLR_EnIB (UL(0x1) << 30)
sys/arm64/include/armreg.h
2651
#define SCTLR_EnIA (UL(0x1) << 31)
sys/arm64/include/armreg.h
2653
#define SCTLR_MSCEn (UL(0x1) << 33)
sys/arm64/include/armreg.h
2655
#define SCTLR_BT0 (UL(0x1) << 35)
sys/arm64/include/armreg.h
2656
#define SCTLR_BT1 (UL(0x1) << 36)
sys/arm64/include/armreg.h
2657
#define SCTLR_ITFSB (UL(0x1) << 37)
sys/arm64/include/armreg.h
2658
#define SCTLR_TCF0_MASK (UL(0x3) << 38)
sys/arm64/include/armreg.h
2659
#define SCTLR_TCF_MASK (UL(0x3) << 40)
sys/arm64/include/armreg.h
2660
#define SCTLR_ATA0 (UL(0x1) << 42)
sys/arm64/include/armreg.h
2661
#define SCTLR_ATA (UL(0x1) << 43)
sys/arm64/include/armreg.h
2662
#define SCTLR_DSSBS (UL(0x1) << 44)
sys/arm64/include/armreg.h
2663
#define SCTLR_TWEDEn (UL(0x1) << 45)
sys/arm64/include/armreg.h
2664
#define SCTLR_TWEDEL_MASK (UL(0xf) << 46)
sys/arm64/include/armreg.h
2666
#define SCTLR_EnASR (UL(0x1) << 54)
sys/arm64/include/armreg.h
2667
#define SCTLR_EnAS0 (UL(0x1) << 55)
sys/arm64/include/armreg.h
2668
#define SCTLR_EnALS (UL(0x1) << 56)
sys/arm64/include/armreg.h
2669
#define SCTLR_EPAN (UL(0x1) << 57)
sys/arm64/include/armreg.h
2778
#define TCR_DS (UL(1) << TCR_DS_SHIFT)
sys/arm64/include/armreg.h
2780
#define TCR_TCMA1 (UL(1) << TCR_TCMA1_SHIFT)
sys/arm64/include/armreg.h
2782
#define TCR_TCMA0 (UL(1) << TCR_TCMA0_SHIFT)
sys/arm64/include/armreg.h
2784
#define TCR_E0PD1 (UL(1) << TCR_E0PD1_SHIFT)
sys/arm64/include/armreg.h
2786
#define TCR_E0PD0 (UL(1) << TCR_E0PD0_SHIFT)
sys/arm64/include/armreg.h
2788
#define TCR_NFD1 (UL(1) << TCR_NFD1_SHIFT)
sys/arm64/include/armreg.h
2790
#define TCR_NFD0 (UL(1) << TCR_NFD0_SHIFT)
sys/arm64/include/armreg.h
2792
#define TCR_TBID1 (UL(1) << TCR_TBID1_SHIFT)
sys/arm64/include/armreg.h
2794
#define TCR_TBID0 (UL(1) << TCR_TBID0_SHIFT)
sys/arm64/include/armreg.h
2796
#define TCR_HWU162 (UL(1) << TCR_HWU162_SHIFT)
sys/arm64/include/armreg.h
2798
#define TCR_HWU161 (UL(1) << TCR_HWU161_SHIFT)
sys/arm64/include/armreg.h
2800
#define TCR_HWU160 (UL(1) << TCR_HWU160_SHIFT)
sys/arm64/include/armreg.h
2802
#define TCR_HWU159 (UL(1) << TCR_HWU159_SHIFT)
sys/arm64/include/armreg.h
2806
#define TCR_HWU062 (UL(1) << TCR_HWU062_SHIFT)
sys/arm64/include/armreg.h
2808
#define TCR_HWU061 (UL(1) << TCR_HWU061_SHIFT)
sys/arm64/include/armreg.h
2810
#define TCR_HWU060 (UL(1) << TCR_HWU060_SHIFT)
sys/arm64/include/armreg.h
2812
#define TCR_HWU059 (UL(1) << TCR_HWU059_SHIFT)
sys/arm64/include/armreg.h
2816
#define TCR_HPD1 (UL(1) << TCR_HPD1_SHIFT)
sys/arm64/include/armreg.h
2818
#define TCR_HPD0 (UL(1) << TCR_HPD0_SHIFT)
sys/arm64/include/armreg.h
2820
#define TCR_HD (UL(1) << TCR_HD_SHIFT)
sys/arm64/include/armreg.h
2822
#define TCR_HA (UL(1) << TCR_HA_SHIFT)
sys/arm64/include/armreg.h
2824
#define TCR_TBI1 (UL(1) << TCR_TBI1_SHIFT)
sys/arm64/include/armreg.h
2826
#define TCR_TBI0 (UL(1) << TCR_TBI0_SHIFT)
sys/arm64/include/armreg.h
2829
#define TCR_ASID_16 (UL(1) << TCR_ASID_SHIFT)
sys/arm64/include/armreg.h
2833
#define TCR_IPS_32BIT (UL(0) << TCR_IPS_SHIFT)
sys/arm64/include/armreg.h
2834
#define TCR_IPS_36BIT (UL(1) << TCR_IPS_SHIFT)
sys/arm64/include/armreg.h
2835
#define TCR_IPS_40BIT (UL(2) << TCR_IPS_SHIFT)
sys/arm64/include/armreg.h
2836
#define TCR_IPS_42BIT (UL(3) << TCR_IPS_SHIFT)
sys/arm64/include/armreg.h
2837
#define TCR_IPS_44BIT (UL(4) << TCR_IPS_SHIFT)
sys/arm64/include/armreg.h
2838
#define TCR_IPS_48BIT (UL(5) << TCR_IPS_SHIFT)
sys/arm64/include/armreg.h
2840
#define TCR_TG1_MASK (UL(3) << TCR_TG1_SHIFT)
sys/arm64/include/armreg.h
2841
#define TCR_TG1_16K (UL(1) << TCR_TG1_SHIFT)
sys/arm64/include/armreg.h
2842
#define TCR_TG1_4K (UL(2) << TCR_TG1_SHIFT)
sys/arm64/include/armreg.h
2843
#define TCR_TG1_64K (UL(3) << TCR_TG1_SHIFT)
sys/arm64/include/armreg.h
2845
#define TCR_SH1_IS (UL(3) << TCR_SH1_SHIFT)
sys/arm64/include/armreg.h
2847
#define TCR_ORGN1_WBWA (UL(1) << TCR_ORGN1_SHIFT)
sys/arm64/include/armreg.h
2849
#define TCR_IRGN1_WBWA (UL(1) << TCR_IRGN1_SHIFT)
sys/arm64/include/armreg.h
2851
#define TCR_EPD1 (UL(1) << TCR_EPD1_SHIFT)
sys/arm64/include/armreg.h
2853
#define TCR_A1 (UL(1) << TCR_A1_SHIFT)
sys/arm64/include/armreg.h
2855
#define TCR_T1SZ_MASK (UL(0x3f) << TCR_T1SZ_SHIFT)
sys/arm64/include/armreg.h
2858
#define TCR_TG0_MASK (UL(3) << TCR_TG0_SHIFT)
sys/arm64/include/armreg.h
2859
#define TCR_TG0_4K (UL(0) << TCR_TG0_SHIFT)
sys/arm64/include/armreg.h
2860
#define TCR_TG0_64K (UL(1) << TCR_TG0_SHIFT)
sys/arm64/include/armreg.h
2861
#define TCR_TG0_16K (UL(2) << TCR_TG0_SHIFT)
sys/arm64/include/armreg.h
2863
#define TCR_SH0_IS (UL(3) << TCR_SH0_SHIFT)
sys/arm64/include/armreg.h
2865
#define TCR_ORGN0_WBWA (UL(1) << TCR_ORGN0_SHIFT)
sys/arm64/include/armreg.h
2867
#define TCR_IRGN0_WBWA (UL(1) << TCR_IRGN0_SHIFT)
sys/arm64/include/armreg.h
2869
#define TCR_EPD0 (UL(1) << TCR_EPD0_SHIFT)
sys/arm64/include/armreg.h
2872
#define TCR_T0SZ_MASK (UL(0x3f) << TCR_T0SZ_SHIFT)
sys/arm64/include/armreg.h
358
#define CTR_TminLine_MASK (UL(0x3f) << CTR_TminLine_SHIFT)
sys/arm64/include/armreg.h
661
#define ESR_ELx_EC_MASK (UL(0x3f) << 26)
sys/arm64/include/armreg.h
793
#define ID_AA64DFR0_DebugVer_MASK (UL(0xf) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
795
#define ID_AA64DFR0_DebugVer_8 (UL(0x6) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
796
#define ID_AA64DFR0_DebugVer_8_VHE (UL(0x7) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
797
#define ID_AA64DFR0_DebugVer_8_2 (UL(0x8) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
798
#define ID_AA64DFR0_DebugVer_8_4 (UL(0x9) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
799
#define ID_AA64DFR0_DebugVer_8_8 (UL(0xa) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
800
#define ID_AA64DFR0_DebugVer_8_9 (UL(0xb) << ID_AA64DFR0_DebugVer_SHIFT)
sys/arm64/include/armreg.h
803
#define ID_AA64DFR0_TraceVer_MASK (UL(0xf) << ID_AA64DFR0_TraceVer_SHIFT)
sys/arm64/include/armreg.h
805
#define ID_AA64DFR0_TraceVer_NONE (UL(0x0) << ID_AA64DFR0_TraceVer_SHIFT)
sys/arm64/include/armreg.h
806
#define ID_AA64DFR0_TraceVer_IMPL (UL(0x1) << ID_AA64DFR0_TraceVer_SHIFT)
sys/arm64/include/armreg.h
809
#define ID_AA64DFR0_PMUVer_MASK (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
811
#define ID_AA64DFR0_PMUVer_NONE (UL(0x0) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
812
#define ID_AA64DFR0_PMUVer_3 (UL(0x1) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
813
#define ID_AA64DFR0_PMUVer_3_1 (UL(0x4) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
814
#define ID_AA64DFR0_PMUVer_3_4 (UL(0x5) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
815
#define ID_AA64DFR0_PMUVer_3_5 (UL(0x6) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
816
#define ID_AA64DFR0_PMUVer_3_7 (UL(0x7) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
817
#define ID_AA64DFR0_PMUVer_3_8 (UL(0x8) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
818
#define ID_AA64DFR0_PMUVer_3_9 (UL(0x9) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
819
#define ID_AA64DFR0_PMUVer_IMPL (UL(0xf) << ID_AA64DFR0_PMUVer_SHIFT)
sys/arm64/include/armreg.h
822
#define ID_AA64DFR0_BRPs_MASK (UL(0xf) << ID_AA64DFR0_BRPs_SHIFT)
sys/arm64/include/armreg.h
827
#define ID_AA64DFR0_PMSS_MASK (UL(0xf) << ID_AA64DFR0_PMSS_SHIFT)
sys/arm64/include/armreg.h
829
#define ID_AA64DFR0_PMSS_NONE (UL(0x0) << ID_AA64DFR0_PMSS_SHIFT)
sys/arm64/include/armreg.h
830
#define ID_AA64DFR0_PMSS_IMPL (UL(0x1) << ID_AA64DFR0_PMSS_SHIFT)
sys/arm64/include/armreg.h
833
#define ID_AA64DFR0_WRPs_MASK (UL(0xf) << ID_AA64DFR0_WRPs_SHIFT)
sys/arm64/include/armreg.h
838
#define ID_AA64DFR0_CTX_CMPs_MASK (UL(0xf) << ID_AA64DFR0_CTX_CMPs_SHIFT)
sys/arm64/include/armreg.h
843
#define ID_AA64DFR0_PMSVer_MASK (UL(0xf) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
845
#define ID_AA64DFR0_PMSVer_NONE (UL(0x0) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
846
#define ID_AA64DFR0_PMSVer_SPE (UL(0x1) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
847
#define ID_AA64DFR0_PMSVer_SPE_1_1 (UL(0x2) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
848
#define ID_AA64DFR0_PMSVer_SPE_1_2 (UL(0x3) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
849
#define ID_AA64DFR0_PMSVer_SPE_1_3 (UL(0x4) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
850
#define ID_AA64DFR0_PMSVer_SPE_1_4 (UL(0x5) << ID_AA64DFR0_PMSVer_SHIFT)
sys/arm64/include/armreg.h
853
#define ID_AA64DFR0_DoubleLock_MASK (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
sys/arm64/include/armreg.h
855
#define ID_AA64DFR0_DoubleLock_IMPL (UL(0x0) << ID_AA64DFR0_DoubleLock_SHIFT)
sys/arm64/include/armreg.h
856
#define ID_AA64DFR0_DoubleLock_NONE (UL(0xf) << ID_AA64DFR0_DoubleLock_SHIFT)
sys/arm64/include/armreg.h
859
#define ID_AA64DFR0_TraceFilt_MASK (UL(0xf) << ID_AA64DFR0_TraceFilt_SHIFT)
sys/arm64/include/armreg.h
861
#define ID_AA64DFR0_TraceFilt_NONE (UL(0x0) << ID_AA64DFR0_TraceFilt_SHIFT)
sys/arm64/include/armreg.h
862
#define ID_AA64DFR0_TraceFilt_8_4 (UL(0x1) << ID_AA64DFR0_TraceFilt_SHIFT)
sys/arm64/include/armreg.h
865
#define ID_AA64DFR0_TraceBuffer_MASK (UL(0xf) << ID_AA64DFR0_TraceBuffer_SHIFT)
sys/arm64/include/armreg.h
867
#define ID_AA64DFR0_TraceBuffer_NONE (UL(0x0) << ID_AA64DFR0_TraceBuffer_SHIFT)
sys/arm64/include/armreg.h
868
#define ID_AA64DFR0_TraceBuffer_IMPL (UL(0x1) << ID_AA64DFR0_TraceBuffer_SHIFT)
sys/arm64/include/armreg.h
871
#define ID_AA64DFR0_MTPMU_MASK (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT)
sys/arm64/include/armreg.h
873
#define ID_AA64DFR0_MTPMU_NONE (UL(0x0) << ID_AA64DFR0_MTPMU_SHIFT)
sys/arm64/include/armreg.h
874
#define ID_AA64DFR0_MTPMU_IMPL (UL(0x1) << ID_AA64DFR0_MTPMU_SHIFT)
sys/arm64/include/armreg.h
875
#define ID_AA64DFR0_MTPMU_NONE_MT_RES0 (UL(0xf) << ID_AA64DFR0_MTPMU_SHIFT)
sys/arm64/include/armreg.h
878
#define ID_AA64DFR0_BRBE_MASK (UL(0xf) << ID_AA64DFR0_BRBE_SHIFT)
sys/arm64/include/armreg.h
880
#define ID_AA64DFR0_BRBE_NONE (UL(0x0) << ID_AA64DFR0_BRBE_SHIFT)
sys/arm64/include/armreg.h
881
#define ID_AA64DFR0_BRBE_IMPL (UL(0x1) << ID_AA64DFR0_BRBE_SHIFT)
sys/arm64/include/armreg.h
882
#define ID_AA64DFR0_BRBE_EL3 (UL(0x2) << ID_AA64DFR0_BRBE_SHIFT)
sys/arm64/include/armreg.h
885
#define ID_AA64DFR0_HPMN0_MASK (UL(0xf) << ID_AA64DFR0_HPMN0_SHIFT)
sys/arm64/include/armreg.h
887
#define ID_AA64DFR0_HPMN0_CONSTR (UL(0x0) << ID_AA64DFR0_HPMN0_SHIFT)
sys/arm64/include/armreg.h
888
#define ID_AA64DFR0_HPMN0_DEFINED (UL(0x1) << ID_AA64DFR0_HPMN0_SHIFT)
sys/arm64/include/armreg.h
900
#define ID_AA64DFR1_SPMU_MASK (UL(0xf) << ID_AA64DFR1_SPMU_SHIFT)
sys/arm64/include/armreg.h
902
#define ID_AA64DFR1_SPMU_NONE (UL(0x0) << ID_AA64DFR1_SPMU_SHIFT)
sys/arm64/include/armreg.h
903
#define ID_AA64DFR1_SPMU_IMPL (UL(0x1) << ID_AA64DFR1_SPMU_SHIFT)
sys/arm64/include/armreg.h
906
#define ID_AA64DFR1_PMICNTR_MASK (UL(0xf) << ID_AA64DFR1_PMICNTR_SHIFT)
sys/arm64/include/armreg.h
908
#define ID_AA64DFR1_PMICNTR_NONE (UL(0x0) << ID_AA64DFR1_PMICNTR_SHIFT)
sys/arm64/include/armreg.h
909
#define ID_AA64DFR1_PMICNTR_IMPL (UL(0x1) << ID_AA64DFR1_PMICNTR_SHIFT)
sys/arm64/include/armreg.h
912
#define ID_AA64DFR1_DPFZS_MASK (UL(0xf) << ID_AA64DFR1_DPFZS_SHIFT)
sys/arm64/include/armreg.h
914
#define ID_AA64DFR1_DPFZS_NONE (UL(0x0) << ID_AA64DFR1_DPFZS_SHIFT)
sys/arm64/include/armreg.h
915
#define ID_AA64DFR1_DPFZS_IMPL (UL(0x1) << ID_AA64DFR1_DPFZS_SHIFT)
sys/arm64/include/armreg.h
927
#define ID_AA64ISAR0_AES_MASK (UL(0xf) << ID_AA64ISAR0_AES_SHIFT)
sys/arm64/include/armreg.h
929
#define ID_AA64ISAR0_AES_NONE (UL(0x0) << ID_AA64ISAR0_AES_SHIFT)
sys/arm64/include/armreg.h
930
#define ID_AA64ISAR0_AES_BASE (UL(0x1) << ID_AA64ISAR0_AES_SHIFT)
sys/arm64/include/armreg.h
931
#define ID_AA64ISAR0_AES_PMULL (UL(0x2) << ID_AA64ISAR0_AES_SHIFT)
sys/arm64/include/armreg.h
934
#define ID_AA64ISAR0_SHA1_MASK (UL(0xf) << ID_AA64ISAR0_SHA1_SHIFT)
sys/arm64/include/armreg.h
936
#define ID_AA64ISAR0_SHA1_NONE (UL(0x0) << ID_AA64ISAR0_SHA1_SHIFT)
sys/arm64/include/armreg.h
937
#define ID_AA64ISAR0_SHA1_BASE (UL(0x1) << ID_AA64ISAR0_SHA1_SHIFT)
sys/arm64/include/armreg.h
940
#define ID_AA64ISAR0_SHA2_MASK (UL(0xf) << ID_AA64ISAR0_SHA2_SHIFT)
sys/arm64/include/armreg.h
942
#define ID_AA64ISAR0_SHA2_NONE (UL(0x0) << ID_AA64ISAR0_SHA2_SHIFT)
sys/arm64/include/armreg.h
943
#define ID_AA64ISAR0_SHA2_BASE (UL(0x1) << ID_AA64ISAR0_SHA2_SHIFT)
sys/arm64/include/armreg.h
944
#define ID_AA64ISAR0_SHA2_512 (UL(0x2) << ID_AA64ISAR0_SHA2_SHIFT)
sys/arm64/include/armreg.h
947
#define ID_AA64ISAR0_CRC32_MASK (UL(0xf) << ID_AA64ISAR0_CRC32_SHIFT)
sys/arm64/include/armreg.h
949
#define ID_AA64ISAR0_CRC32_NONE (UL(0x0) << ID_AA64ISAR0_CRC32_SHIFT)
sys/arm64/include/armreg.h
950
#define ID_AA64ISAR0_CRC32_BASE (UL(0x1) << ID_AA64ISAR0_CRC32_SHIFT)
sys/arm64/include/armreg.h
953
#define ID_AA64ISAR0_Atomic_MASK (UL(0xf) << ID_AA64ISAR0_Atomic_SHIFT)
sys/arm64/include/armreg.h
955
#define ID_AA64ISAR0_Atomic_NONE (UL(0x0) << ID_AA64ISAR0_Atomic_SHIFT)
sys/arm64/include/armreg.h
956
#define ID_AA64ISAR0_Atomic_IMPL (UL(0x2) << ID_AA64ISAR0_Atomic_SHIFT)
sys/arm64/include/armreg.h
959
#define ID_AA64ISAR0_TME_MASK (UL(0xf) << ID_AA64ISAR0_TME_SHIFT)
sys/arm64/include/armreg.h
960
#define ID_AA64ISAR0_TME_NONE (UL(0x0) << ID_AA64ISAR0_TME_SHIFT)
sys/arm64/include/armreg.h
961
#define ID_AA64ISAR0_TME_IMPL (UL(0x1) << ID_AA64ISAR0_TME_SHIFT)
sys/arm64/include/armreg.h
964
#define ID_AA64ISAR0_RDM_MASK (UL(0xf) << ID_AA64ISAR0_RDM_SHIFT)
sys/arm64/include/armreg.h
966
#define ID_AA64ISAR0_RDM_NONE (UL(0x0) << ID_AA64ISAR0_RDM_SHIFT)
sys/arm64/include/armreg.h
967
#define ID_AA64ISAR0_RDM_IMPL (UL(0x1) << ID_AA64ISAR0_RDM_SHIFT)
sys/arm64/include/armreg.h
970
#define ID_AA64ISAR0_SHA3_MASK (UL(0xf) << ID_AA64ISAR0_SHA3_SHIFT)
sys/arm64/include/armreg.h
972
#define ID_AA64ISAR0_SHA3_NONE (UL(0x0) << ID_AA64ISAR0_SHA3_SHIFT)
sys/arm64/include/armreg.h
973
#define ID_AA64ISAR0_SHA3_IMPL (UL(0x1) << ID_AA64ISAR0_SHA3_SHIFT)
sys/arm64/include/armreg.h
976
#define ID_AA64ISAR0_SM3_MASK (UL(0xf) << ID_AA64ISAR0_SM3_SHIFT)
sys/arm64/include/armreg.h
978
#define ID_AA64ISAR0_SM3_NONE (UL(0x0) << ID_AA64ISAR0_SM3_SHIFT)
sys/arm64/include/armreg.h
979
#define ID_AA64ISAR0_SM3_IMPL (UL(0x1) << ID_AA64ISAR0_SM3_SHIFT)
sys/arm64/include/armreg.h
982
#define ID_AA64ISAR0_SM4_MASK (UL(0xf) << ID_AA64ISAR0_SM4_SHIFT)
sys/arm64/include/armreg.h
984
#define ID_AA64ISAR0_SM4_NONE (UL(0x0) << ID_AA64ISAR0_SM4_SHIFT)
sys/arm64/include/armreg.h
985
#define ID_AA64ISAR0_SM4_IMPL (UL(0x1) << ID_AA64ISAR0_SM4_SHIFT)
sys/arm64/include/armreg.h
988
#define ID_AA64ISAR0_DP_MASK (UL(0xf) << ID_AA64ISAR0_DP_SHIFT)
sys/arm64/include/armreg.h
990
#define ID_AA64ISAR0_DP_NONE (UL(0x0) << ID_AA64ISAR0_DP_SHIFT)
sys/arm64/include/armreg.h
991
#define ID_AA64ISAR0_DP_IMPL (UL(0x1) << ID_AA64ISAR0_DP_SHIFT)
sys/arm64/include/armreg.h
994
#define ID_AA64ISAR0_FHM_MASK (UL(0xf) << ID_AA64ISAR0_FHM_SHIFT)
sys/arm64/include/armreg.h
996
#define ID_AA64ISAR0_FHM_NONE (UL(0x0) << ID_AA64ISAR0_FHM_SHIFT)
sys/arm64/include/armreg.h
997
#define ID_AA64ISAR0_FHM_IMPL (UL(0x1) << ID_AA64ISAR0_FHM_SHIFT)
sys/arm64/include/hypervisor.h
1000
#define HDFGWTR_EL2_DBGPRCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1001
#define HDFGWTR_EL2_DBGPRCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1003
#define HDFGWTR_EL2_DBGCLAIM_MASK (UL(0x1) << HDFGWTR_EL2_DBGCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
1005
#define HDFGWTR_EL2_DBGCLAIM_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
1006
#define HDFGWTR_EL2_DBGCLAIM_TRAP (UL(0x1) << HDFGWTR_EL2_DBGCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
1008
#define HDFGWTR_EL2_MDSCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_MDSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1010
#define HDFGWTR_EL2_MDSCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_MDSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1011
#define HDFGWTR_EL2_MDSCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_MDSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1013
#define HDFGWTR_EL2_DBGWVRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1015
#define HDFGWTR_EL2_DBGWVRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1016
#define HDFGWTR_EL2_DBGWVRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGWVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1018
#define HDFGWTR_EL2_DBGWCRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1020
#define HDFGWTR_EL2_DBGWCRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1021
#define HDFGWTR_EL2_DBGWCRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGWCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1023
#define HDFGWTR_EL2_DBGBVRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1025
#define HDFGWTR_EL2_DBGBVRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1026
#define HDFGWTR_EL2_DBGBVRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGBVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1028
#define HDFGWTR_EL2_DBGBCRn_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1030
#define HDFGWTR_EL2_DBGBCRn_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1031
#define HDFGWTR_EL2_DBGBCRn_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_DBGBCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1049
#define HFGITR_EL2_ATS1E1A_MASK (UL(0x1) << HFGITR_EL2_ATS1E1A_SHIFT)
sys/arm64/include/hypervisor.h
1051
#define HFGITR_EL2_ATS1E1A_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1A_SHIFT)
sys/arm64/include/hypervisor.h
1052
#define HFGITR_EL2_ATS1E1A_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1A_SHIFT)
sys/arm64/include/hypervisor.h
1054
#define HFGITR_EL2_COSPRCTX_MASK (UL(0x1) << HFGITR_EL2_COSPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1056
#define HFGITR_EL2_COSPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_COSPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1057
#define HFGITR_EL2_COSPRCTX_TRAP (UL(0x1) << HFGITR_EL2_COSPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1059
#define HFGITR_EL2_nGCSEPP_MASK (UL(0x1) << HFGITR_EL2_nGCSEPP_SHIFT)
sys/arm64/include/hypervisor.h
1061
#define HFGITR_EL2_nGCSEPP_TRAP (UL(0x0) << HFGITR_EL2_nGCSEPP_SHIFT)
sys/arm64/include/hypervisor.h
1062
#define HFGITR_EL2_nGCSEPP_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSEPP_SHIFT)
sys/arm64/include/hypervisor.h
1064
#define HFGITR_EL2_nGCSSTR_EL1_MASK (UL(0x1) << HFGITR_EL2_nGCSSTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1066
#define HFGITR_EL2_nGCSSTR_EL1_TRAP (UL(0x0) << HFGITR_EL2_nGCSSTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1067
#define HFGITR_EL2_nGCSSTR_EL1_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSSTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1069
#define HFGITR_EL2_nGCSPUSHM_EL1_MASK (UL(0x1) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1071
#define HFGITR_EL2_nGCSPUSHM_EL1_TRAP (UL(0x0) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1072
#define HFGITR_EL2_nGCSPUSHM_EL1_NOTRAP (UL(0x1) << HFGITR_EL2_nGCSPUSHM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1074
#define HFGITR_EL2_nBRBIALL_MASK (UL(0x1) << HFGITR_EL2_nBRBIALL_SHIFT)
sys/arm64/include/hypervisor.h
1076
#define HFGITR_EL2_nBRBIALL_TRAP (UL(0x0) << HFGITR_EL2_nBRBIALL_SHIFT)
sys/arm64/include/hypervisor.h
1077
#define HFGITR_EL2_nBRBIALL_NOTRAP (UL(0x1) << HFGITR_EL2_nBRBIALL_SHIFT)
sys/arm64/include/hypervisor.h
1079
#define HFGITR_EL2_nBRBINJ_MASK (UL(0x1) << HFGITR_EL2_nBRBINJ_SHIFT)
sys/arm64/include/hypervisor.h
1081
#define HFGITR_EL2_nBRBINJ_TRAP (UL(0x0) << HFGITR_EL2_nBRBINJ_SHIFT)
sys/arm64/include/hypervisor.h
1082
#define HFGITR_EL2_nBRBINJ_NOTRAP (UL(0x1) << HFGITR_EL2_nBRBINJ_SHIFT)
sys/arm64/include/hypervisor.h
1084
#define HFGITR_EL2_DCCVAC_MASK (UL(0x1) << HFGITR_EL2_DCCVAC_SHIFT)
sys/arm64/include/hypervisor.h
1086
#define HFGITR_EL2_DCCVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAC_SHIFT)
sys/arm64/include/hypervisor.h
1087
#define HFGITR_EL2_DCCVAC_TRAP (UL(0x1) << HFGITR_EL2_DCCVAC_SHIFT)
sys/arm64/include/hypervisor.h
1089
#define HFGITR_EL2_SVC_EL1_MASK (UL(0x1) << HFGITR_EL2_SVC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1091
#define HFGITR_EL2_SVC_EL1_NOTRAP (UL(0x0) << HFGITR_EL2_SVC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1092
#define HFGITR_EL2_SVC_EL1_TRAP (UL(0x1) << HFGITR_EL2_SVC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1094
#define HFGITR_EL2_SVC_EL0_MASK (UL(0x1) << HFGITR_EL2_SVC_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1096
#define HFGITR_EL2_SVC_EL0_NOTRAP (UL(0x0) << HFGITR_EL2_SVC_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1097
#define HFGITR_EL2_SVC_EL0_TRAP (UL(0x1) << HFGITR_EL2_SVC_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1099
#define HFGITR_EL2_ERET_MASK (UL(0x1) << HFGITR_EL2_ERET_SHIFT)
sys/arm64/include/hypervisor.h
1101
#define HFGITR_EL2_ERET_NOTRAP (UL(0x0) << HFGITR_EL2_ERET_SHIFT)
sys/arm64/include/hypervisor.h
1102
#define HFGITR_EL2_ERET_TRAP (UL(0x1) << HFGITR_EL2_ERET_SHIFT)
sys/arm64/include/hypervisor.h
1104
#define HFGITR_EL2_CPPRCTX_MASK (UL(0x1) << HFGITR_EL2_CPPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1106
#define HFGITR_EL2_CPPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_CPPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1107
#define HFGITR_EL2_CPPRCTX_TRAP (UL(0x1) << HFGITR_EL2_CPPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1109
#define HFGITR_EL2_DVPRCTX_MASK (UL(0x1) << HFGITR_EL2_DVPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1111
#define HFGITR_EL2_DVPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_DVPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1112
#define HFGITR_EL2_DVPRCTX_TRAP (UL(0x1) << HFGITR_EL2_DVPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1114
#define HFGITR_EL2_CFPRCTX_MASK (UL(0x1) << HFGITR_EL2_CFPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1116
#define HFGITR_EL2_CFPRCTX_NOTRAP (UL(0x0) << HFGITR_EL2_CFPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1117
#define HFGITR_EL2_CFPRCTX_TRAP (UL(0x1) << HFGITR_EL2_CFPRCTX_SHIFT)
sys/arm64/include/hypervisor.h
1119
#define HFGITR_EL2_TLBIVAALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1_SHIFT)
sys/arm64/include/hypervisor.h
1121
#define HFGITR_EL2_TLBIVAALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1_SHIFT)
sys/arm64/include/hypervisor.h
1122
#define HFGITR_EL2_TLBIVAALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1_SHIFT)
sys/arm64/include/hypervisor.h
1124
#define HFGITR_EL2_TLBIVALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1_SHIFT)
sys/arm64/include/hypervisor.h
1126
#define HFGITR_EL2_TLBIVALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1_SHIFT)
sys/arm64/include/hypervisor.h
1127
#define HFGITR_EL2_TLBIVALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1_SHIFT)
sys/arm64/include/hypervisor.h
1129
#define HFGITR_EL2_TLBIVAAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1_SHIFT)
sys/arm64/include/hypervisor.h
1131
#define HFGITR_EL2_TLBIVAAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1_SHIFT)
sys/arm64/include/hypervisor.h
1132
#define HFGITR_EL2_TLBIVAAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1_SHIFT)
sys/arm64/include/hypervisor.h
1134
#define HFGITR_EL2_TLBIASIDE1_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1_SHIFT)
sys/arm64/include/hypervisor.h
1136
#define HFGITR_EL2_TLBIASIDE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1_SHIFT)
sys/arm64/include/hypervisor.h
1137
#define HFGITR_EL2_TLBIASIDE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1_SHIFT)
sys/arm64/include/hypervisor.h
1139
#define HFGITR_EL2_TLBIVAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1_SHIFT)
sys/arm64/include/hypervisor.h
1141
#define HFGITR_EL2_TLBIVAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1_SHIFT)
sys/arm64/include/hypervisor.h
1142
#define HFGITR_EL2_TLBIVAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1_SHIFT)
sys/arm64/include/hypervisor.h
1144
#define HFGITR_EL2_TLBIVMALLE1_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1_SHIFT)
sys/arm64/include/hypervisor.h
1146
#define HFGITR_EL2_TLBIVMALLE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1_SHIFT)
sys/arm64/include/hypervisor.h
1147
#define HFGITR_EL2_TLBIVMALLE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1_SHIFT)
sys/arm64/include/hypervisor.h
1149
#define HFGITR_EL2_TLBIRVAALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1_SHIFT)
sys/arm64/include/hypervisor.h
1151
#define HFGITR_EL2_TLBIRVAALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1_SHIFT)
sys/arm64/include/hypervisor.h
1152
#define HFGITR_EL2_TLBIRVAALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1_SHIFT)
sys/arm64/include/hypervisor.h
1154
#define HFGITR_EL2_TLBIRVALE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1_SHIFT)
sys/arm64/include/hypervisor.h
1156
#define HFGITR_EL2_TLBIRVALE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1_SHIFT)
sys/arm64/include/hypervisor.h
1157
#define HFGITR_EL2_TLBIRVALE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1_SHIFT)
sys/arm64/include/hypervisor.h
1159
#define HFGITR_EL2_TLBIRVAAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1_SHIFT)
sys/arm64/include/hypervisor.h
1161
#define HFGITR_EL2_TLBIRVAAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1_SHIFT)
sys/arm64/include/hypervisor.h
1162
#define HFGITR_EL2_TLBIRVAAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1_SHIFT)
sys/arm64/include/hypervisor.h
1164
#define HFGITR_EL2_TLBIRVAE1_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1_SHIFT)
sys/arm64/include/hypervisor.h
1166
#define HFGITR_EL2_TLBIRVAE1_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1_SHIFT)
sys/arm64/include/hypervisor.h
1167
#define HFGITR_EL2_TLBIRVAE1_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1_SHIFT)
sys/arm64/include/hypervisor.h
1169
#define HFGITR_EL2_TLBIRVAALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1171
#define HFGITR_EL2_TLBIRVAALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1172
#define HFGITR_EL2_TLBIRVAALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1174
#define HFGITR_EL2_TLBIRVALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1176
#define HFGITR_EL2_TLBIRVALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1177
#define HFGITR_EL2_TLBIRVALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1179
#define HFGITR_EL2_TLBIRVAAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1181
#define HFGITR_EL2_TLBIRVAAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1182
#define HFGITR_EL2_TLBIRVAAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1184
#define HFGITR_EL2_TLBIRVAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1186
#define HFGITR_EL2_TLBIRVAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1187
#define HFGITR_EL2_TLBIRVAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1189
#define HFGITR_EL2_TLBIVAALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1191
#define HFGITR_EL2_TLBIVAALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1192
#define HFGITR_EL2_TLBIVAALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1194
#define HFGITR_EL2_TLBIVALE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1196
#define HFGITR_EL2_TLBIVALE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1197
#define HFGITR_EL2_TLBIVALE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1199
#define HFGITR_EL2_TLBIVAAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1201
#define HFGITR_EL2_TLBIVAAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1202
#define HFGITR_EL2_TLBIVAAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1204
#define HFGITR_EL2_TLBIASIDE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1206
#define HFGITR_EL2_TLBIASIDE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1207
#define HFGITR_EL2_TLBIASIDE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1209
#define HFGITR_EL2_TLBIVAE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1211
#define HFGITR_EL2_TLBIVAE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1212
#define HFGITR_EL2_TLBIVAE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1214
#define HFGITR_EL2_TLBIVMALLE1IS_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1216
#define HFGITR_EL2_TLBIVMALLE1IS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1217
#define HFGITR_EL2_TLBIVMALLE1IS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1IS_SHIFT)
sys/arm64/include/hypervisor.h
1219
#define HFGITR_EL2_TLBIRVAALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1221
#define HFGITR_EL2_TLBIRVAALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1222
#define HFGITR_EL2_TLBIRVAALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1224
#define HFGITR_EL2_TLBIRVALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1226
#define HFGITR_EL2_TLBIRVALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1227
#define HFGITR_EL2_TLBIRVALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1229
#define HFGITR_EL2_TLBIRVAAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1231
#define HFGITR_EL2_TLBIRVAAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1232
#define HFGITR_EL2_TLBIRVAAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1234
#define HFGITR_EL2_TLBIRVAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIRVAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1236
#define HFGITR_EL2_TLBIRVAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIRVAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1237
#define HFGITR_EL2_TLBIRVAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIRVAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1239
#define HFGITR_EL2_TLBIVAALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1241
#define HFGITR_EL2_TLBIVAALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1242
#define HFGITR_EL2_TLBIVAALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1244
#define HFGITR_EL2_TLBIVALE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1246
#define HFGITR_EL2_TLBIVALE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1247
#define HFGITR_EL2_TLBIVALE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVALE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1249
#define HFGITR_EL2_TLBIVAAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1251
#define HFGITR_EL2_TLBIVAAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1252
#define HFGITR_EL2_TLBIVAAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1254
#define HFGITR_EL2_TLBIASIDE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIASIDE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1256
#define HFGITR_EL2_TLBIASIDE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIASIDE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1257
#define HFGITR_EL2_TLBIASIDE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIASIDE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1259
#define HFGITR_EL2_TLBIVAE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1261
#define HFGITR_EL2_TLBIVAE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1262
#define HFGITR_EL2_TLBIVAE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVAE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1264
#define HFGITR_EL2_TLBIVMALLE1OS_MASK (UL(0x1) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1266
#define HFGITR_EL2_TLBIVMALLE1OS_NOTRAP (UL(0x0) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1267
#define HFGITR_EL2_TLBIVMALLE1OS_TRAP (UL(0x1) << HFGITR_EL2_TLBIVMALLE1OS_SHIFT)
sys/arm64/include/hypervisor.h
1269
#define HFGITR_EL2_ATS1E1WP_MASK (UL(0x1) << HFGITR_EL2_ATS1E1WP_SHIFT)
sys/arm64/include/hypervisor.h
1271
#define HFGITR_EL2_ATS1E1WP_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1WP_SHIFT)
sys/arm64/include/hypervisor.h
1272
#define HFGITR_EL2_ATS1E1WP_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1WP_SHIFT)
sys/arm64/include/hypervisor.h
1274
#define HFGITR_EL2_ATS1E1RP_MASK (UL(0x1) << HFGITR_EL2_ATS1E1RP_SHIFT)
sys/arm64/include/hypervisor.h
1276
#define HFGITR_EL2_ATS1E1RP_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1RP_SHIFT)
sys/arm64/include/hypervisor.h
1277
#define HFGITR_EL2_ATS1E1RP_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1RP_SHIFT)
sys/arm64/include/hypervisor.h
1279
#define HFGITR_EL2_ATS1E0W_MASK (UL(0x1) << HFGITR_EL2_ATS1E0W_SHIFT)
sys/arm64/include/hypervisor.h
1281
#define HFGITR_EL2_ATS1E0W_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E0W_SHIFT)
sys/arm64/include/hypervisor.h
1282
#define HFGITR_EL2_ATS1E0W_TRAP (UL(0x1) << HFGITR_EL2_ATS1E0W_SHIFT)
sys/arm64/include/hypervisor.h
1284
#define HFGITR_EL2_ATS1E0R_MASK (UL(0x1) << HFGITR_EL2_ATS1E0R_SHIFT)
sys/arm64/include/hypervisor.h
1286
#define HFGITR_EL2_ATS1E0R_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E0R_SHIFT)
sys/arm64/include/hypervisor.h
1287
#define HFGITR_EL2_ATS1E0R_TRAP (UL(0x1) << HFGITR_EL2_ATS1E0R_SHIFT)
sys/arm64/include/hypervisor.h
1289
#define HFGITR_EL2_ATS1E1W_MASK (UL(0x1) << HFGITR_EL2_ATS1E1W_SHIFT)
sys/arm64/include/hypervisor.h
1291
#define HFGITR_EL2_ATS1E1W_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1W_SHIFT)
sys/arm64/include/hypervisor.h
1292
#define HFGITR_EL2_ATS1E1W_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1W_SHIFT)
sys/arm64/include/hypervisor.h
1294
#define HFGITR_EL2_ATS1E1R_MASK (UL(0x1) << HFGITR_EL2_ATS1E1R_SHIFT)
sys/arm64/include/hypervisor.h
1296
#define HFGITR_EL2_ATS1E1R_NOTRAP (UL(0x0) << HFGITR_EL2_ATS1E1R_SHIFT)
sys/arm64/include/hypervisor.h
1297
#define HFGITR_EL2_ATS1E1R_TRAP (UL(0x1) << HFGITR_EL2_ATS1E1R_SHIFT)
sys/arm64/include/hypervisor.h
1299
#define HFGITR_EL2_DCZVA_MASK (UL(0x1) << HFGITR_EL2_DCZVA_SHIFT)
sys/arm64/include/hypervisor.h
1301
#define HFGITR_EL2_DCZVA_NOTRAP (UL(0x0) << HFGITR_EL2_DCZVA_SHIFT)
sys/arm64/include/hypervisor.h
1302
#define HFGITR_EL2_DCZVA_TRAP (UL(0x1) << HFGITR_EL2_DCZVA_SHIFT)
sys/arm64/include/hypervisor.h
1304
#define HFGITR_EL2_DCCIVAC_MASK (UL(0x1) << HFGITR_EL2_DCCIVAC_SHIFT)
sys/arm64/include/hypervisor.h
1306
#define HFGITR_EL2_DCCIVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCCIVAC_SHIFT)
sys/arm64/include/hypervisor.h
1307
#define HFGITR_EL2_DCCIVAC_TRAP (UL(0x1) << HFGITR_EL2_DCCIVAC_SHIFT)
sys/arm64/include/hypervisor.h
1309
#define HFGITR_EL2_DCCVADP_MASK (UL(0x1) << HFGITR_EL2_DCCVADP_SHIFT)
sys/arm64/include/hypervisor.h
1311
#define HFGITR_EL2_DCCVADP_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVADP_SHIFT)
sys/arm64/include/hypervisor.h
1312
#define HFGITR_EL2_DCCVADP_TRAP (UL(0x1) << HFGITR_EL2_DCCVADP_SHIFT)
sys/arm64/include/hypervisor.h
1314
#define HFGITR_EL2_DCCVAP_MASK (UL(0x1) << HFGITR_EL2_DCCVAP_SHIFT)
sys/arm64/include/hypervisor.h
1316
#define HFGITR_EL2_DCCVAP_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAP_SHIFT)
sys/arm64/include/hypervisor.h
1317
#define HFGITR_EL2_DCCVAP_TRAP (UL(0x1) << HFGITR_EL2_DCCVAP_SHIFT)
sys/arm64/include/hypervisor.h
1319
#define HFGITR_EL2_DCCVAU_MASK (UL(0x1) << HFGITR_EL2_DCCVAU_SHIFT)
sys/arm64/include/hypervisor.h
1321
#define HFGITR_EL2_DCCVAU_NOTRAP (UL(0x0) << HFGITR_EL2_DCCVAU_SHIFT)
sys/arm64/include/hypervisor.h
1322
#define HFGITR_EL2_DCCVAU_TRAP (UL(0x1) << HFGITR_EL2_DCCVAU_SHIFT)
sys/arm64/include/hypervisor.h
1324
#define HFGITR_EL2_DCCISW_MASK (UL(0x1) << HFGITR_EL2_DCCISW_SHIFT)
sys/arm64/include/hypervisor.h
1326
#define HFGITR_EL2_DCCISW_NOTRAP (UL(0x0) << HFGITR_EL2_DCCISW_SHIFT)
sys/arm64/include/hypervisor.h
1327
#define HFGITR_EL2_DCCISW_TRAP (UL(0x1) << HFGITR_EL2_DCCISW_SHIFT)
sys/arm64/include/hypervisor.h
1329
#define HFGITR_EL2_DCCSW_MASK (UL(0x1) << HFGITR_EL2_DCCSW_SHIFT)
sys/arm64/include/hypervisor.h
1331
#define HFGITR_EL2_DCCSW_NOTRAP (UL(0x0) << HFGITR_EL2_DCCSW_SHIFT)
sys/arm64/include/hypervisor.h
1332
#define HFGITR_EL2_DCCSW_TRAP (UL(0x1) << HFGITR_EL2_DCCSW_SHIFT)
sys/arm64/include/hypervisor.h
1334
#define HFGITR_EL2_DCISW_MASK (UL(0x1) << HFGITR_EL2_DCISW_SHIFT)
sys/arm64/include/hypervisor.h
1336
#define HFGITR_EL2_DCISW_NOTRAP (UL(0x0) << HFGITR_EL2_DCISW_SHIFT)
sys/arm64/include/hypervisor.h
1337
#define HFGITR_EL2_DCISW_TRAP (UL(0x1) << HFGITR_EL2_DCISW_SHIFT)
sys/arm64/include/hypervisor.h
1339
#define HFGITR_EL2_DCIVAC_MASK (UL(0x1) << HFGITR_EL2_DCIVAC_SHIFT)
sys/arm64/include/hypervisor.h
1341
#define HFGITR_EL2_DCIVAC_NOTRAP (UL(0x0) << HFGITR_EL2_DCIVAC_SHIFT)
sys/arm64/include/hypervisor.h
1342
#define HFGITR_EL2_DCIVAC_TRAP (UL(0x1) << HFGITR_EL2_DCIVAC_SHIFT)
sys/arm64/include/hypervisor.h
1344
#define HFGITR_EL2_ICIVAU_MASK (UL(0x1) << HFGITR_EL2_ICIVAU_SHIFT)
sys/arm64/include/hypervisor.h
1346
#define HFGITR_EL2_ICIVAU_NOTRAP (UL(0x0) << HFGITR_EL2_ICIVAU_SHIFT)
sys/arm64/include/hypervisor.h
1347
#define HFGITR_EL2_ICIVAU_TRAP (UL(0x1) << HFGITR_EL2_ICIVAU_SHIFT)
sys/arm64/include/hypervisor.h
1349
#define HFGITR_EL2_ICIALLU_MASK (UL(0x1) << HFGITR_EL2_ICIALLU_SHIFT)
sys/arm64/include/hypervisor.h
1351
#define HFGITR_EL2_ICIALLU_NOTRAP (UL(0x0) << HFGITR_EL2_ICIALLU_SHIFT)
sys/arm64/include/hypervisor.h
1352
#define HFGITR_EL2_ICIALLU_TRAP (UL(0x1) << HFGITR_EL2_ICIALLU_SHIFT)
sys/arm64/include/hypervisor.h
1354
#define HFGITR_EL2_ICIALLUIS_MASK (UL(0x1) << HFGITR_EL2_ICIALLUIS_SHIFT)
sys/arm64/include/hypervisor.h
1356
#define HFGITR_EL2_ICIALLUIS_NOTRAP (UL(0x0) << HFGITR_EL2_ICIALLUIS_SHIFT)
sys/arm64/include/hypervisor.h
1357
#define HFGITR_EL2_ICIALLUIS_TRAP (UL(0x1) << HFGITR_EL2_ICIALLUIS_SHIFT)
sys/arm64/include/hypervisor.h
1367
#define HFGRTR2_EL2_nRCWSMASK_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1369
#define HFGRTR2_EL2_nRCWSMASK_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1370
#define HFGRTR2_EL2_nRCWSMASK_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nRCWSMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1372
#define HFGRTR2_EL2_nERXGSR_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1374
#define HFGRTR2_EL2_nERXGSR_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1375
#define HFGRTR2_EL2_nERXGSR_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nERXGSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1377
#define HFGRTR2_EL2_nPFAR_EL1_MASK (UL(0x1) << HFGRTR2_EL2_nPFAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1379
#define HFGRTR2_EL2_nPFAR_EL1_TRAP (UL(0x0) << HFGRTR2_EL2_nPFAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1380
#define HFGRTR2_EL2_nPFAR_EL1_NOTRAP (UL(0x1) << HFGRTR2_EL2_nPFAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1390
#define HFGRTR_EL2_nAMAIR2_EL1_MASK (UL(0x1) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1392
#define HFGRTR_EL2_nAMAIR2_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1393
#define HFGRTR_EL2_nAMAIR2_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nAMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1395
#define HFGRTR_EL2_nMAIR2_EL1_MASK (UL(0x1) << HFGRTR_EL2_nMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1397
#define HFGRTR_EL2_nMAIR2_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1398
#define HFGRTR_EL2_nMAIR2_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1400
#define HFGRTR_EL2_nS2POR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nS2POR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1402
#define HFGRTR_EL2_nS2POR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nS2POR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1403
#define HFGRTR_EL2_nS2POR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nS2POR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1405
#define HFGRTR_EL2_nPOR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPOR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1407
#define HFGRTR_EL2_nPOR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPOR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1408
#define HFGRTR_EL2_nPOR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPOR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1410
#define HFGRTR_EL2_nPOR_EL0_MASK (UL(0x1) << HFGRTR_EL2_nPOR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1412
#define HFGRTR_EL2_nPOR_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nPOR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1413
#define HFGRTR_EL2_nPOR_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nPOR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1415
#define HFGRTR_EL2_nPIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1417
#define HFGRTR_EL2_nPIR_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1418
#define HFGRTR_EL2_nPIR_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1420
#define HFGRTR_EL2_nPIRE0_EL1_MASK (UL(0x1) << HFGRTR_EL2_nPIRE0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1422
#define HFGRTR_EL2_nPIRE0_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nPIRE0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1423
#define HFGRTR_EL2_nPIRE0_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nPIRE0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1425
#define HFGRTR_EL2_nRCWMASK_EL1_MASK (UL(0x1) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1427
#define HFGRTR_EL2_nRCWMASK_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1428
#define HFGRTR_EL2_nRCWMASK_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nRCWMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1430
#define HFGRTR_EL2_nTPIDR2_EL0_MASK (UL(0x1) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1432
#define HFGRTR_EL2_nTPIDR2_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1433
#define HFGRTR_EL2_nTPIDR2_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nTPIDR2_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1435
#define HFGRTR_EL2_nSMPRI_EL1_MASK (UL(0x1) << HFGRTR_EL2_nSMPRI_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1437
#define HFGRTR_EL2_nSMPRI_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nSMPRI_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1438
#define HFGRTR_EL2_nSMPRI_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nSMPRI_EL1_SHIFT)
sys/arm64/include/hypervisor.h
144
#define HAFGRTR_EL2_TRAP_ALL UL(0x0003fffffffe001f)
sys/arm64/include/hypervisor.h
1440
#define HFGRTR_EL2_nGCS_EL1_MASK (UL(0x1) << HFGRTR_EL2_nGCS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1442
#define HFGRTR_EL2_nGCS_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nGCS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1443
#define HFGRTR_EL2_nGCS_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nGCS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1445
#define HFGRTR_EL2_nGCS_EL0_MASK (UL(0x1) << HFGRTR_EL2_nGCS_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1447
#define HFGRTR_EL2_nGCS_EL0_TRAP (UL(0x0) << HFGRTR_EL2_nGCS_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1448
#define HFGRTR_EL2_nGCS_EL0_NOTRAP (UL(0x1) << HFGRTR_EL2_nGCS_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1450
#define HFGRTR_EL2_nACCDATA_EL1_MASK (UL(0x1) << HFGRTR_EL2_nACCDATA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1452
#define HFGRTR_EL2_nACCDATA_EL1_TRAP (UL(0x0) << HFGRTR_EL2_nACCDATA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1453
#define HFGRTR_EL2_nACCDATA_EL1_NOTRAP (UL(0x1) << HFGRTR_EL2_nACCDATA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1455
#define HFGRTR_EL2_ERXADDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXADDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1457
#define HFGRTR_EL2_ERXADDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXADDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1458
#define HFGRTR_EL2_ERXADDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXADDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1460
#define HFGRTR_EL2_ERXPFGCDN_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1462
#define HFGRTR_EL2_ERXPFGCDN_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1463
#define HFGRTR_EL2_ERXPFGCDN_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGCDN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1465
#define HFGRTR_EL2_ERXPFGCTL_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1467
#define HFGRTR_EL2_ERXPFGCTL_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1468
#define HFGRTR_EL2_ERXPFGCTL_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGCTL_EL1_SHIFT)
sys/arm64/include/hypervisor.h
147
#define HCR_VM (UL(0x1) << 0)
sys/arm64/include/hypervisor.h
1470
#define HFGRTR_EL2_ERXPFGF_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1472
#define HFGRTR_EL2_ERXPFGF_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1473
#define HFGRTR_EL2_ERXPFGF_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXPFGF_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1475
#define HFGRTR_EL2_ERXMISCn_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1477
#define HFGRTR_EL2_ERXMISCn_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1478
#define HFGRTR_EL2_ERXMISCn_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXMISCn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
148
#define HCR_SWIO (UL(0x1) << 1)
sys/arm64/include/hypervisor.h
1480
#define HFGRTR_EL2_ERXSTATUS_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1482
#define HFGRTR_EL2_ERXSTATUS_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1483
#define HFGRTR_EL2_ERXSTATUS_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1485
#define HFGRTR_EL2_ERXCTLR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1487
#define HFGRTR_EL2_ERXCTLR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1488
#define HFGRTR_EL2_ERXCTLR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
149
#define HCR_PTW (UL(0x1) << 2)
sys/arm64/include/hypervisor.h
1490
#define HFGRTR_EL2_ERXFR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERXFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1492
#define HFGRTR_EL2_ERXFR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERXFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1493
#define HFGRTR_EL2_ERXFR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERXFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1495
#define HFGRTR_EL2_ERRSELR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERRSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1497
#define HFGRTR_EL2_ERRSELR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERRSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1498
#define HFGRTR_EL2_ERRSELR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERRSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
150
#define HCR_FMO (UL(0x1) << 3)
sys/arm64/include/hypervisor.h
1500
#define HFGRTR_EL2_ERRIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ERRIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1502
#define HFGRTR_EL2_ERRIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ERRIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1503
#define HFGRTR_EL2_ERRIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ERRIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1505
#define HFGRTR_EL2_ICC_IGRPENn_EL1_MASK (UL(0x1) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1507
#define HFGRTR_EL2_ICC_IGRPENn_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1508
#define HFGRTR_EL2_ICC_IGRPENn_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ICC_IGRPENn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
151
#define HCR_IMO (UL(0x1) << 4)
sys/arm64/include/hypervisor.h
1510
#define HFGRTR_EL2_VBAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_VBAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1512
#define HFGRTR_EL2_VBAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_VBAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1513
#define HFGRTR_EL2_VBAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_VBAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1515
#define HFGRTR_EL2_TTBR1_EL1_MASK (UL(0x1) << HFGRTR_EL2_TTBR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1517
#define HFGRTR_EL2_TTBR1_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TTBR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1518
#define HFGRTR_EL2_TTBR1_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TTBR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
152
#define HCR_AMO (UL(0x1) << 5)
sys/arm64/include/hypervisor.h
1520
#define HFGRTR_EL2_TTBR0_EL1_MASK (UL(0x1) << HFGRTR_EL2_TTBR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1522
#define HFGRTR_EL2_TTBR0_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TTBR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1523
#define HFGRTR_EL2_TTBR0_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TTBR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1525
#define HFGRTR_EL2_TPIDR_EL0_MASK (UL(0x1) << HFGRTR_EL2_TPIDR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1527
#define HFGRTR_EL2_TPIDR_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1528
#define HFGRTR_EL2_TPIDR_EL0_TRAP (UL(0x1) << HFGRTR_EL2_TPIDR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
153
#define HCR_VF (UL(0x1) << 6)
sys/arm64/include/hypervisor.h
1530
#define HFGRTR_EL2_TPIDRRO_EL0_MASK (UL(0x1) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1532
#define HFGRTR_EL2_TPIDRRO_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1533
#define HFGRTR_EL2_TPIDRRO_EL0_TRAP (UL(0x1) << HFGRTR_EL2_TPIDRRO_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1535
#define HFGRTR_EL2_TPIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_TPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1537
#define HFGRTR_EL2_TPIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1538
#define HFGRTR_EL2_TPIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
154
#define HCR_VI (UL(0x1) << 7)
sys/arm64/include/hypervisor.h
1540
#define HFGRTR_EL2_TCR_EL1_MASK (UL(0x1) << HFGRTR_EL2_TCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1542
#define HFGRTR_EL2_TCR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_TCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1543
#define HFGRTR_EL2_TCR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_TCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1545
#define HFGRTR_EL2_SCXTNUM_EL0_MASK (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1547
#define HFGRTR_EL2_SCXTNUM_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1548
#define HFGRTR_EL2_SCXTNUM_EL0_TRAP (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL0_SHIFT)
sys/arm64/include/hypervisor.h
155
#define HCR_VSE (UL(0x1) << 8)
sys/arm64/include/hypervisor.h
1550
#define HFGRTR_EL2_SCXTNUM_EL1_MASK (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1552
#define HFGRTR_EL2_SCXTNUM_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1553
#define HFGRTR_EL2_SCXTNUM_EL1_TRAP (UL(0x1) << HFGRTR_EL2_SCXTNUM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1555
#define HFGRTR_EL2_SCTLR_EL1_MASK (UL(0x1) << HFGRTR_EL2_SCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1557
#define HFGRTR_EL2_SCTLR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_SCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1558
#define HFGRTR_EL2_SCTLR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_SCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
156
#define HCR_FB (UL(0x1) << 9)
sys/arm64/include/hypervisor.h
1560
#define HFGRTR_EL2_REVIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_REVIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1562
#define HFGRTR_EL2_REVIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_REVIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1563
#define HFGRTR_EL2_REVIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_REVIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1565
#define HFGRTR_EL2_PAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_PAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1567
#define HFGRTR_EL2_PAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_PAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1568
#define HFGRTR_EL2_PAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_PAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
157
#define HCR_BSU_MASK (UL(0x3) << 10)
sys/arm64/include/hypervisor.h
1570
#define HFGRTR_EL2_MPIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1572
#define HFGRTR_EL2_MPIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1573
#define HFGRTR_EL2_MPIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1575
#define HFGRTR_EL2_MIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1577
#define HFGRTR_EL2_MIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1578
#define HFGRTR_EL2_MIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
158
#define HCR_BSU_IS (UL(0x1) << 10)
sys/arm64/include/hypervisor.h
1580
#define HFGRTR_EL2_MAIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_MAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1582
#define HFGRTR_EL2_MAIR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_MAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1583
#define HFGRTR_EL2_MAIR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_MAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1585
#define HFGRTR_EL2_LORSA_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORSA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1587
#define HFGRTR_EL2_LORSA_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORSA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1588
#define HFGRTR_EL2_LORSA_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORSA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
159
#define HCR_BSU_OS (UL(0x2) << 10)
sys/arm64/include/hypervisor.h
1590
#define HFGRTR_EL2_LORN_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1592
#define HFGRTR_EL2_LORN_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1593
#define HFGRTR_EL2_LORN_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1595
#define HFGRTR_EL2_LORID_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORID_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1597
#define HFGRTR_EL2_LORID_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORID_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1598
#define HFGRTR_EL2_LORID_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORID_EL1_SHIFT)
sys/arm64/include/hypervisor.h
160
#define HCR_BSU_FS (UL(0x3) << 10)
sys/arm64/include/hypervisor.h
1600
#define HFGRTR_EL2_LOREA_EL1_MASK (UL(0x1) << HFGRTR_EL2_LOREA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1602
#define HFGRTR_EL2_LOREA_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LOREA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1603
#define HFGRTR_EL2_LOREA_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LOREA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1605
#define HFGRTR_EL2_LORC_EL1_MASK (UL(0x1) << HFGRTR_EL2_LORC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1607
#define HFGRTR_EL2_LORC_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_LORC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1608
#define HFGRTR_EL2_LORC_EL1_TRAP (UL(0x1) << HFGRTR_EL2_LORC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
161
#define HCR_DC (UL(0x1) << 12)
sys/arm64/include/hypervisor.h
1610
#define HFGRTR_EL2_ISR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ISR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1612
#define HFGRTR_EL2_ISR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ISR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1613
#define HFGRTR_EL2_ISR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ISR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1615
#define HFGRTR_EL2_FAR_EL1_MASK (UL(0x1) << HFGRTR_EL2_FAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1617
#define HFGRTR_EL2_FAR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_FAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1618
#define HFGRTR_EL2_FAR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_FAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
162
#define HCR_TWI (UL(0x1) << 13)
sys/arm64/include/hypervisor.h
1620
#define HFGRTR_EL2_ESR_EL1_MASK (UL(0x1) << HFGRTR_EL2_ESR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1622
#define HFGRTR_EL2_ESR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_ESR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1623
#define HFGRTR_EL2_ESR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_ESR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1625
#define HFGRTR_EL2_DCZID_EL0_MASK (UL(0x1) << HFGRTR_EL2_DCZID_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1627
#define HFGRTR_EL2_DCZID_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_DCZID_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1628
#define HFGRTR_EL2_DCZID_EL0_TRAP (UL(0x1) << HFGRTR_EL2_DCZID_EL0_SHIFT)
sys/arm64/include/hypervisor.h
163
#define HCR_TWE (UL(0x1) << 14)
sys/arm64/include/hypervisor.h
1630
#define HFGRTR_EL2_CTR_EL0_MASK (UL(0x1) << HFGRTR_EL2_CTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1632
#define HFGRTR_EL2_CTR_EL0_NOTRAP (UL(0x0) << HFGRTR_EL2_CTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1633
#define HFGRTR_EL2_CTR_EL0_TRAP (UL(0x1) << HFGRTR_EL2_CTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1635
#define HFGRTR_EL2_CSSELR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CSSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1637
#define HFGRTR_EL2_CSSELR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CSSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1638
#define HFGRTR_EL2_CSSELR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CSSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
164
#define HCR_TID0 (UL(0x1) << 15)
sys/arm64/include/hypervisor.h
1640
#define HFGRTR_EL2_CPACR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CPACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1642
#define HFGRTR_EL2_CPACR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CPACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1643
#define HFGRTR_EL2_CPACR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CPACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1645
#define HFGRTR_EL2_CONTEXTIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1647
#define HFGRTR_EL2_CONTEXTIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1648
#define HFGRTR_EL2_CONTEXTIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CONTEXTIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
165
#define HCR_TID1 (UL(0x1) << 16)
sys/arm64/include/hypervisor.h
1650
#define HFGRTR_EL2_CLIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CLIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1652
#define HFGRTR_EL2_CLIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CLIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1653
#define HFGRTR_EL2_CLIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CLIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1655
#define HFGRTR_EL2_CCSIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_CCSIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1657
#define HFGRTR_EL2_CCSIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_CCSIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1658
#define HFGRTR_EL2_CCSIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_CCSIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
166
#define HCR_TID2 (UL(0x1) << 17)
sys/arm64/include/hypervisor.h
1660
#define HFGRTR_EL2_APIBKey_MASK (UL(0x1) << HFGRTR_EL2_APIBKey_SHIFT)
sys/arm64/include/hypervisor.h
1662
#define HFGRTR_EL2_APIBKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APIBKey_SHIFT)
sys/arm64/include/hypervisor.h
1663
#define HFGRTR_EL2_APIBKey_TRAP (UL(0x1) << HFGRTR_EL2_APIBKey_SHIFT)
sys/arm64/include/hypervisor.h
1665
#define HFGRTR_EL2_APIAKey_MASK (UL(0x1) << HFGRTR_EL2_APIAKey_SHIFT)
sys/arm64/include/hypervisor.h
1667
#define HFGRTR_EL2_APIAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APIAKey_SHIFT)
sys/arm64/include/hypervisor.h
1668
#define HFGRTR_EL2_APIAKey_TRAP (UL(0x1) << HFGRTR_EL2_APIAKey_SHIFT)
sys/arm64/include/hypervisor.h
167
#define HCR_TID3 (UL(0x1) << 18)
sys/arm64/include/hypervisor.h
1670
#define HFGRTR_EL2_APGAKey_MASK (UL(0x1) << HFGRTR_EL2_APGAKey_SHIFT)
sys/arm64/include/hypervisor.h
1672
#define HFGRTR_EL2_APGAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APGAKey_SHIFT)
sys/arm64/include/hypervisor.h
1673
#define HFGRTR_EL2_APGAKey_TRAP (UL(0x1) << HFGRTR_EL2_APGAKey_SHIFT)
sys/arm64/include/hypervisor.h
1675
#define HFGRTR_EL2_APDBKey_MASK (UL(0x1) << HFGRTR_EL2_APDBKey_SHIFT)
sys/arm64/include/hypervisor.h
1677
#define HFGRTR_EL2_APDBKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APDBKey_SHIFT)
sys/arm64/include/hypervisor.h
1678
#define HFGRTR_EL2_APDBKey_TRAP (UL(0x1) << HFGRTR_EL2_APDBKey_SHIFT)
sys/arm64/include/hypervisor.h
168
#define HCR_TSC (UL(0x1) << 19)
sys/arm64/include/hypervisor.h
1680
#define HFGRTR_EL2_APDAKey_MASK (UL(0x1) << HFGRTR_EL2_APDAKey_SHIFT)
sys/arm64/include/hypervisor.h
1682
#define HFGRTR_EL2_APDAKey_NOTRAP (UL(0x0) << HFGRTR_EL2_APDAKey_SHIFT)
sys/arm64/include/hypervisor.h
1683
#define HFGRTR_EL2_APDAKey_TRAP (UL(0x1) << HFGRTR_EL2_APDAKey_SHIFT)
sys/arm64/include/hypervisor.h
1685
#define HFGRTR_EL2_AMAIR_EL1_MASK (UL(0x1) << HFGRTR_EL2_AMAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1687
#define HFGRTR_EL2_AMAIR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AMAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1688
#define HFGRTR_EL2_AMAIR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AMAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
169
#define HCR_TIDCP (UL(0x1) << 20)
sys/arm64/include/hypervisor.h
1690
#define HFGRTR_EL2_AIDR_EL1_MASK (UL(0x1) << HFGRTR_EL2_AIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1692
#define HFGRTR_EL2_AIDR_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1693
#define HFGRTR_EL2_AIDR_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1695
#define HFGRTR_EL2_AFSR1_EL1_MASK (UL(0x1) << HFGRTR_EL2_AFSR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1697
#define HFGRTR_EL2_AFSR1_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AFSR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1698
#define HFGRTR_EL2_AFSR1_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AFSR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
170
#define HCR_TACR (UL(0x1) << 21)
sys/arm64/include/hypervisor.h
1700
#define HFGRTR_EL2_AFSR0_EL1_MASK (UL(0x1) << HFGRTR_EL2_AFSR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1702
#define HFGRTR_EL2_AFSR0_EL1_NOTRAP (UL(0x0) << HFGRTR_EL2_AFSR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1703
#define HFGRTR_EL2_AFSR0_EL1_TRAP (UL(0x1) << HFGRTR_EL2_AFSR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
171
#define HCR_TSW (UL(0x1) << 22)
sys/arm64/include/hypervisor.h
1713
#define HFGWTR2_EL2_nRCWSMASK_EL1_MASK (UL(0x1) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1715
#define HFGWTR2_EL2_nRCWSMASK_EL1_TRAP (UL(0x0) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1716
#define HFGWTR2_EL2_nRCWSMASK_EL1_NOTRAP (UL(0x1) << HFGWTR2_EL2_nRCWSMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1718
#define HFGWTR2_EL2_nPFAR_EL1_MASK (UL(0x1) << HFGWTR2_EL2_nPFAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
172
#define HCR_TPCP (UL(0x1) << 23)
sys/arm64/include/hypervisor.h
1720
#define HFGWTR2_EL2_nPFAR_EL1_TRAP (UL(0x0) << HFGWTR2_EL2_nPFAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1721
#define HFGWTR2_EL2_nPFAR_EL1_NOTRAP (UL(0x1) << HFGWTR2_EL2_nPFAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
173
#define HCR_TPU (UL(0x1) << 24)
sys/arm64/include/hypervisor.h
1731
#define HFGWTR_EL2_nAMAIR2_EL1_MASK (UL(0x1) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1733
#define HFGWTR_EL2_nAMAIR2_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1734
#define HFGWTR_EL2_nAMAIR2_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nAMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1736
#define HFGWTR_EL2_nMAIR2_EL1_MASK (UL(0x1) << HFGWTR_EL2_nMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1738
#define HFGWTR_EL2_nMAIR2_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1739
#define HFGWTR_EL2_nMAIR2_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nMAIR2_EL1_SHIFT)
sys/arm64/include/hypervisor.h
174
#define HCR_TTLB (UL(0x1) << 25)
sys/arm64/include/hypervisor.h
1741
#define HFGWTR_EL2_nS2POR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nS2POR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1743
#define HFGWTR_EL2_nS2POR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nS2POR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1744
#define HFGWTR_EL2_nS2POR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nS2POR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1746
#define HFGWTR_EL2_nPOR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPOR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1748
#define HFGWTR_EL2_nPOR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPOR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1749
#define HFGWTR_EL2_nPOR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPOR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
175
#define HCR_TVM (UL(0x1) << 26)
sys/arm64/include/hypervisor.h
1751
#define HFGWTR_EL2_nPOR_EL0_MASK (UL(0x1) << HFGWTR_EL2_nPOR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1753
#define HFGWTR_EL2_nPOR_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nPOR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1754
#define HFGWTR_EL2_nPOR_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nPOR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1756
#define HFGWTR_EL2_nPIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1758
#define HFGWTR_EL2_nPIR_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1759
#define HFGWTR_EL2_nPIR_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
176
#define HCR_TGE (UL(0x1) << 27)
sys/arm64/include/hypervisor.h
1761
#define HFGWTR_EL2_nPIRE0_EL1_MASK (UL(0x1) << HFGWTR_EL2_nPIRE0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1763
#define HFGWTR_EL2_nPIRE0_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nPIRE0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1764
#define HFGWTR_EL2_nPIRE0_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nPIRE0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1766
#define HFGWTR_EL2_nRCWMASK_EL1_MASK (UL(0x1) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1768
#define HFGWTR_EL2_nRCWMASK_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1769
#define HFGWTR_EL2_nRCWMASK_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nRCWMASK_EL1_SHIFT)
sys/arm64/include/hypervisor.h
177
#define HCR_TDZ (UL(0x1) << 28)
sys/arm64/include/hypervisor.h
1771
#define HFGWTR_EL2_nTPIDR2_EL0_MASK (UL(0x1) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1773
#define HFGWTR_EL2_nTPIDR2_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1774
#define HFGWTR_EL2_nTPIDR2_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nTPIDR2_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1776
#define HFGWTR_EL2_nSMPRI_EL1_MASK (UL(0x1) << HFGWTR_EL2_nSMPRI_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1778
#define HFGWTR_EL2_nSMPRI_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nSMPRI_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1779
#define HFGWTR_EL2_nSMPRI_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nSMPRI_EL1_SHIFT)
sys/arm64/include/hypervisor.h
178
#define HCR_HCD (UL(0x1) << 29)
sys/arm64/include/hypervisor.h
1781
#define HFGWTR_EL2_nGCS_EL1_MASK (UL(0x1) << HFGWTR_EL2_nGCS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1783
#define HFGWTR_EL2_nGCS_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nGCS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1784
#define HFGWTR_EL2_nGCS_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nGCS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1786
#define HFGWTR_EL2_nGCS_EL0_MASK (UL(0x1) << HFGWTR_EL2_nGCS_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1788
#define HFGWTR_EL2_nGCS_EL0_TRAP (UL(0x0) << HFGWTR_EL2_nGCS_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1789
#define HFGWTR_EL2_nGCS_EL0_NOTRAP (UL(0x1) << HFGWTR_EL2_nGCS_EL0_SHIFT)
sys/arm64/include/hypervisor.h
179
#define HCR_TRVM (UL(0x1) << 30)
sys/arm64/include/hypervisor.h
1791
#define HFGWTR_EL2_nACCDATA_EL1_MASK (UL(0x1) << HFGWTR_EL2_nACCDATA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1793
#define HFGWTR_EL2_nACCDATA_EL1_TRAP (UL(0x0) << HFGWTR_EL2_nACCDATA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1794
#define HFGWTR_EL2_nACCDATA_EL1_NOTRAP (UL(0x1) << HFGWTR_EL2_nACCDATA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1796
#define HFGWTR_EL2_ERXADDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXADDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1798
#define HFGWTR_EL2_ERXADDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXADDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1799
#define HFGWTR_EL2_ERXADDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXADDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
180
#define HCR_RW (UL(0x1) << 31)
sys/arm64/include/hypervisor.h
1801
#define HFGWTR_EL2_ERXPFGCDN_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1803
#define HFGWTR_EL2_ERXPFGCDN_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1804
#define HFGWTR_EL2_ERXPFGCDN_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXPFGCDN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1806
#define HFGWTR_EL2_ERXPFGCTL_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1808
#define HFGWTR_EL2_ERXPFGCTL_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1809
#define HFGWTR_EL2_ERXPFGCTL_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXPFGCTL_EL1_SHIFT)
sys/arm64/include/hypervisor.h
181
#define HCR_CD (UL(0x1) << 32)
sys/arm64/include/hypervisor.h
1811
#define HFGWTR_EL2_ERXMISCn_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1813
#define HFGWTR_EL2_ERXMISCn_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1814
#define HFGWTR_EL2_ERXMISCn_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXMISCn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1816
#define HFGWTR_EL2_ERXSTATUS_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1818
#define HFGWTR_EL2_ERXSTATUS_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1819
#define HFGWTR_EL2_ERXSTATUS_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
182
#define HCR_ID (UL(0x1) << 33)
sys/arm64/include/hypervisor.h
1821
#define HFGWTR_EL2_ERXCTLR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1823
#define HFGWTR_EL2_ERXCTLR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1824
#define HFGWTR_EL2_ERXCTLR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERXCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1826
#define HFGWTR_EL2_ERRSELR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ERRSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1828
#define HFGWTR_EL2_ERRSELR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ERRSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1829
#define HFGWTR_EL2_ERRSELR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ERRSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
183
#define HCR_E2H (UL(0x1) << 34)
sys/arm64/include/hypervisor.h
1831
#define HFGWTR_EL2_ICC_IGRPENn_EL1_MASK (UL(0x1) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1833
#define HFGWTR_EL2_ICC_IGRPENn_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1834
#define HFGWTR_EL2_ICC_IGRPENn_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ICC_IGRPENn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1836
#define HFGWTR_EL2_VBAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_VBAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1838
#define HFGWTR_EL2_VBAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_VBAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1839
#define HFGWTR_EL2_VBAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_VBAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
184
#define HCR_TLOR (UL(0x1) << 35)
sys/arm64/include/hypervisor.h
1841
#define HFGWTR_EL2_TTBR1_EL1_MASK (UL(0x1) << HFGWTR_EL2_TTBR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1843
#define HFGWTR_EL2_TTBR1_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TTBR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1844
#define HFGWTR_EL2_TTBR1_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TTBR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1846
#define HFGWTR_EL2_TTBR0_EL1_MASK (UL(0x1) << HFGWTR_EL2_TTBR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1848
#define HFGWTR_EL2_TTBR0_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TTBR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1849
#define HFGWTR_EL2_TTBR0_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TTBR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
185
#define HCR_TERR (UL(0x1) << 36)
sys/arm64/include/hypervisor.h
1851
#define HFGWTR_EL2_TPIDR_EL0_MASK (UL(0x1) << HFGWTR_EL2_TPIDR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1853
#define HFGWTR_EL2_TPIDR_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1854
#define HFGWTR_EL2_TPIDR_EL0_TRAP (UL(0x1) << HFGWTR_EL2_TPIDR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1856
#define HFGWTR_EL2_TPIDRRO_EL0_MASK (UL(0x1) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1858
#define HFGWTR_EL2_TPIDRRO_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1859
#define HFGWTR_EL2_TPIDRRO_EL0_TRAP (UL(0x1) << HFGWTR_EL2_TPIDRRO_EL0_SHIFT)
sys/arm64/include/hypervisor.h
186
#define HCR_TEA (UL(0x1) << 37)
sys/arm64/include/hypervisor.h
1861
#define HFGWTR_EL2_TPIDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_TPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1863
#define HFGWTR_EL2_TPIDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1864
#define HFGWTR_EL2_TPIDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TPIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1866
#define HFGWTR_EL2_TCR_EL1_MASK (UL(0x1) << HFGWTR_EL2_TCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1868
#define HFGWTR_EL2_TCR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_TCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1869
#define HFGWTR_EL2_TCR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_TCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
187
#define HCR_MIOCNCE (UL(0x1) << 38)
sys/arm64/include/hypervisor.h
1871
#define HFGWTR_EL2_SCXTNUM_EL0_MASK (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1873
#define HFGWTR_EL2_SCXTNUM_EL0_NOTRAP (UL(0x0) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1874
#define HFGWTR_EL2_SCXTNUM_EL0_TRAP (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL0_SHIFT)
sys/arm64/include/hypervisor.h
1876
#define HFGWTR_EL2_SCXTNUM_EL1_MASK (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1878
#define HFGWTR_EL2_SCXTNUM_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1879
#define HFGWTR_EL2_SCXTNUM_EL1_TRAP (UL(0x1) << HFGWTR_EL2_SCXTNUM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1881
#define HFGWTR_EL2_SCTLR_EL1_MASK (UL(0x1) << HFGWTR_EL2_SCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1883
#define HFGWTR_EL2_SCTLR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_SCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1884
#define HFGWTR_EL2_SCTLR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_SCTLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1886
#define HFGWTR_EL2_PAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_PAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1888
#define HFGWTR_EL2_PAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_PAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1889
#define HFGWTR_EL2_PAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_PAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
189
#define HCR_APK (UL(0x1) << 40)
sys/arm64/include/hypervisor.h
1891
#define HFGWTR_EL2_MAIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_MAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1893
#define HFGWTR_EL2_MAIR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_MAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1894
#define HFGWTR_EL2_MAIR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_MAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1896
#define HFGWTR_EL2_LORSA_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORSA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1898
#define HFGWTR_EL2_LORSA_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORSA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1899
#define HFGWTR_EL2_LORSA_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORSA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
190
#define HCR_API (UL(0x1) << 41)
sys/arm64/include/hypervisor.h
1901
#define HFGWTR_EL2_LORN_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1903
#define HFGWTR_EL2_LORN_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1904
#define HFGWTR_EL2_LORN_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORN_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1906
#define HFGWTR_EL2_LOREA_EL1_MASK (UL(0x1) << HFGWTR_EL2_LOREA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1908
#define HFGWTR_EL2_LOREA_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LOREA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1909
#define HFGWTR_EL2_LOREA_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LOREA_EL1_SHIFT)
sys/arm64/include/hypervisor.h
191
#define HCR_NV (UL(0x1) << 42)
sys/arm64/include/hypervisor.h
1911
#define HFGWTR_EL2_LORC_EL1_MASK (UL(0x1) << HFGWTR_EL2_LORC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1913
#define HFGWTR_EL2_LORC_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_LORC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1914
#define HFGWTR_EL2_LORC_EL1_TRAP (UL(0x1) << HFGWTR_EL2_LORC_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1916
#define HFGWTR_EL2_FAR_EL1_MASK (UL(0x1) << HFGWTR_EL2_FAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1918
#define HFGWTR_EL2_FAR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_FAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1919
#define HFGWTR_EL2_FAR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_FAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
192
#define HCR_NV1 (UL(0x1) << 43)
sys/arm64/include/hypervisor.h
1921
#define HFGWTR_EL2_ESR_EL1_MASK (UL(0x1) << HFGWTR_EL2_ESR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1923
#define HFGWTR_EL2_ESR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_ESR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1924
#define HFGWTR_EL2_ESR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_ESR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1926
#define HFGWTR_EL2_CSSELR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CSSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1928
#define HFGWTR_EL2_CSSELR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CSSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1929
#define HFGWTR_EL2_CSSELR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CSSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
193
#define HCR_AT (UL(0x1) << 44)
sys/arm64/include/hypervisor.h
1931
#define HFGWTR_EL2_CPACR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CPACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1933
#define HFGWTR_EL2_CPACR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CPACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1934
#define HFGWTR_EL2_CPACR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CPACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1936
#define HFGWTR_EL2_CONTEXTIDR_EL1_MASK (UL(0x1) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1938
#define HFGWTR_EL2_CONTEXTIDR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1939
#define HFGWTR_EL2_CONTEXTIDR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_CONTEXTIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
194
#define HCR_NV2 (UL(0x1) << 45)
sys/arm64/include/hypervisor.h
1941
#define HFGWTR_EL2_APIBKey_MASK (UL(0x1) << HFGWTR_EL2_APIBKey_SHIFT)
sys/arm64/include/hypervisor.h
1943
#define HFGWTR_EL2_APIBKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APIBKey_SHIFT)
sys/arm64/include/hypervisor.h
1944
#define HFGWTR_EL2_APIBKey_TRAP (UL(0x1) << HFGWTR_EL2_APIBKey_SHIFT)
sys/arm64/include/hypervisor.h
1946
#define HFGWTR_EL2_APIAKey_MASK (UL(0x1) << HFGWTR_EL2_APIAKey_SHIFT)
sys/arm64/include/hypervisor.h
1948
#define HFGWTR_EL2_APIAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APIAKey_SHIFT)
sys/arm64/include/hypervisor.h
1949
#define HFGWTR_EL2_APIAKey_TRAP (UL(0x1) << HFGWTR_EL2_APIAKey_SHIFT)
sys/arm64/include/hypervisor.h
195
#define HCR_FWB (UL(0x1) << 46)
sys/arm64/include/hypervisor.h
1951
#define HFGWTR_EL2_APGAKey_MASK (UL(0x1) << HFGWTR_EL2_APGAKey_SHIFT)
sys/arm64/include/hypervisor.h
1953
#define HFGWTR_EL2_APGAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APGAKey_SHIFT)
sys/arm64/include/hypervisor.h
1954
#define HFGWTR_EL2_APGAKey_TRAP (UL(0x1) << HFGWTR_EL2_APGAKey_SHIFT)
sys/arm64/include/hypervisor.h
1956
#define HFGWTR_EL2_APDBKey_MASK (UL(0x1) << HFGWTR_EL2_APDBKey_SHIFT)
sys/arm64/include/hypervisor.h
1958
#define HFGWTR_EL2_APDBKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APDBKey_SHIFT)
sys/arm64/include/hypervisor.h
1959
#define HFGWTR_EL2_APDBKey_TRAP (UL(0x1) << HFGWTR_EL2_APDBKey_SHIFT)
sys/arm64/include/hypervisor.h
196
#define HCR_FIEN (UL(0x1) << 47)
sys/arm64/include/hypervisor.h
1961
#define HFGWTR_EL2_APDAKey_MASK (UL(0x1) << HFGWTR_EL2_APDAKey_SHIFT)
sys/arm64/include/hypervisor.h
1963
#define HFGWTR_EL2_APDAKey_NOTRAP (UL(0x0) << HFGWTR_EL2_APDAKey_SHIFT)
sys/arm64/include/hypervisor.h
1964
#define HFGWTR_EL2_APDAKey_TRAP (UL(0x1) << HFGWTR_EL2_APDAKey_SHIFT)
sys/arm64/include/hypervisor.h
1966
#define HFGWTR_EL2_AMAIR_EL1_MASK (UL(0x1) << HFGWTR_EL2_AMAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1968
#define HFGWTR_EL2_AMAIR_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AMAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1969
#define HFGWTR_EL2_AMAIR_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AMAIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1971
#define HFGWTR_EL2_AFSR1_EL1_MASK (UL(0x1) << HFGWTR_EL2_AFSR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1973
#define HFGWTR_EL2_AFSR1_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AFSR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1974
#define HFGWTR_EL2_AFSR1_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AFSR1_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1976
#define HFGWTR_EL2_AFSR0_EL1_MASK (UL(0x1) << HFGWTR_EL2_AFSR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1978
#define HFGWTR_EL2_AFSR0_EL1_NOTRAP (UL(0x0) << HFGWTR_EL2_AFSR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
1979
#define HFGWTR_EL2_AFSR0_EL1_TRAP (UL(0x1) << HFGWTR_EL2_AFSR0_EL1_SHIFT)
sys/arm64/include/hypervisor.h
198
#define HCR_TID4 (UL(0x1) << 49)
sys/arm64/include/hypervisor.h
199
#define HCR_TICAB (UL(0x1) << 50)
sys/arm64/include/hypervisor.h
200
#define HCR_AMVOFFEN (UL(0x1) << 51)
sys/arm64/include/hypervisor.h
201
#define HCR_TOCU (UL(0x1) << 52)
sys/arm64/include/hypervisor.h
202
#define HCR_EnSCXT (UL(0x1) << 53)
sys/arm64/include/hypervisor.h
203
#define HCR_TTLBIS (UL(0x1) << 54)
sys/arm64/include/hypervisor.h
204
#define HCR_TTLBOS (UL(0x1) << 55)
sys/arm64/include/hypervisor.h
205
#define HCR_ATA (UL(0x1) << 56)
sys/arm64/include/hypervisor.h
206
#define HCR_DCT (UL(0x1) << 57)
sys/arm64/include/hypervisor.h
207
#define HCR_TID5 (UL(0x1) << 58)
sys/arm64/include/hypervisor.h
208
#define HCR_TWEDEn (UL(0x1) << 59)
sys/arm64/include/hypervisor.h
209
#define HCR_TWEDEL_MASK (UL(0xf) << 60)
sys/arm64/include/hypervisor.h
219
#define HCRX_EnAS0 (UL(0x1) << 0)
sys/arm64/include/hypervisor.h
220
#define HCRX_EnALS (UL(0x1) << 1)
sys/arm64/include/hypervisor.h
221
#define HCRX_EnASR (UL(0x1) << 2)
sys/arm64/include/hypervisor.h
222
#define HCRX_FnXS (UL(0x1) << 3)
sys/arm64/include/hypervisor.h
223
#define HCRX_FGTnXS (UL(0x1) << 4)
sys/arm64/include/hypervisor.h
224
#define HCRX_SMPME (UL(0x1) << 5)
sys/arm64/include/hypervisor.h
225
#define HCRX_TALLINT (UL(0x1) << 6)
sys/arm64/include/hypervisor.h
226
#define HCRX_VINMI (UL(0x1) << 7)
sys/arm64/include/hypervisor.h
227
#define HCRX_VFNMI (UL(0x1) << 8)
sys/arm64/include/hypervisor.h
228
#define HCRX_CMOW (UL(0x1) << 9)
sys/arm64/include/hypervisor.h
229
#define HCRX_MCE2 (UL(0x1) << 10)
sys/arm64/include/hypervisor.h
230
#define HCRX_MSCEn (UL(0x1) << 11)
sys/arm64/include/hypervisor.h
232
#define HCRX_TCR2En (UL(0x1) << 14)
sys/arm64/include/hypervisor.h
233
#define HCRX_SCTLR2En (UL(0x1) << 15)
sys/arm64/include/hypervisor.h
234
#define HCRX_PTTWI (UL(0x1) << 16)
sys/arm64/include/hypervisor.h
235
#define HCRX_D128En (UL(0x1) << 17)
sys/arm64/include/hypervisor.h
236
#define HCRX_EnSNERR (UL(0x1) << 18)
sys/arm64/include/hypervisor.h
237
#define HCRX_TMEA (UL(0x1) << 19)
sys/arm64/include/hypervisor.h
238
#define HCRX_EnSDERR (UL(0x1) << 20)
sys/arm64/include/hypervisor.h
239
#define HCRX_EnIDCP128 (UL(0x1) << 21)
sys/arm64/include/hypervisor.h
240
#define HCRX_GCSEn (UL(0x1) << 22)
sys/arm64/include/hypervisor.h
241
#define HCRX_EnFPM (UL(0x1) << 23)
sys/arm64/include/hypervisor.h
242
#define HCRX_PACMEn (UL(0x1) << 24)
sys/arm64/include/hypervisor.h
244
#define HCRX_SRMASKEn (UL(0x1) << 26)
sys/arm64/include/hypervisor.h
254
#define HDFGRTR2_EL2_nMDSTEPOP_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT)
sys/arm64/include/hypervisor.h
256
#define HDFGRTR2_EL2_nMDSTEPOP_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT)
sys/arm64/include/hypervisor.h
257
#define HDFGRTR2_EL2_nMDSTEPOP_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nMDSTEPOP_EL1_SHIFT)
sys/arm64/include/hypervisor.h
259
#define HDFGRTR2_EL2_nTRBMPAM_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
261
#define HDFGRTR2_EL2_nTRBMPAM_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
262
#define HDFGRTR2_EL2_nTRBMPAM_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nTRBMPAM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
264
#define HDFGRTR2_EL2_nTRCITECR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
266
#define HDFGRTR2_EL2_nTRCITECR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
267
#define HDFGRTR2_EL2_nTRCITECR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nTRCITECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
269
#define HDFGRTR2_EL2_nPMSDSFR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
271
#define HDFGRTR2_EL2_nPMSDSFR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
272
#define HDFGRTR2_EL2_nPMSDSFR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSDSFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
274
#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT)
sys/arm64/include/hypervisor.h
276
#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT)
sys/arm64/include/hypervisor.h
277
#define HDFGRTR2_EL2_nSPMDEVAFF_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMDEVAFF_EL1_SHIFT)
sys/arm64/include/hypervisor.h
279
#define HDFGRTR2_EL2_nSPMID_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMID_SHIFT)
sys/arm64/include/hypervisor.h
281
#define HDFGRTR2_EL2_nSPMID_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMID_SHIFT)
sys/arm64/include/hypervisor.h
282
#define HDFGRTR2_EL2_nSPMID_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMID_SHIFT)
sys/arm64/include/hypervisor.h
284
#define HDFGRTR2_EL2_nSPMSCR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
286
#define HDFGRTR2_EL2_nSPMSCR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
287
#define HDFGRTR2_EL2_nSPMSCR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
289
#define HDFGRTR2_EL2_nSPMACCESSR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
291
#define HDFGRTR2_EL2_nSPMACCESSR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
292
#define HDFGRTR2_EL2_nSPMACCESSR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMACCESSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
294
#define HDFGRTR2_EL2_nSPMCR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
296
#define HDFGRTR2_EL2_nSPMCR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
297
#define HDFGRTR2_EL2_nSPMCR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
299
#define HDFGRTR2_EL2_nSPMOVS_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMOVS_SHIFT)
sys/arm64/include/hypervisor.h
301
#define HDFGRTR2_EL2_nSPMOVS_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMOVS_SHIFT)
sys/arm64/include/hypervisor.h
302
#define HDFGRTR2_EL2_nSPMOVS_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMOVS_SHIFT)
sys/arm64/include/hypervisor.h
304
#define HDFGRTR2_EL2_nSPMINTEN_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
306
#define HDFGRTR2_EL2_nSPMINTEN_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
307
#define HDFGRTR2_EL2_nSPMINTEN_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
309
#define HDFGRTR2_EL2_nSPMCNTEN_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
311
#define HDFGRTR2_EL2_nSPMCNTEN_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
312
#define HDFGRTR2_EL2_nSPMCNTEN_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
314
#define HDFGRTR2_EL2_nSPMSELR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
316
#define HDFGRTR2_EL2_nSPMSELR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
317
#define HDFGRTR2_EL2_nSPMSELR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
319
#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
321
#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
322
#define HDFGRTR2_EL2_nSPMEVTYPERn_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
324
#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
326
#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
327
#define HDFGRTR2_EL2_nSPMEVCNTRn_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nSPMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
329
#define HDFGRTR2_EL2_nPMSSCR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
331
#define HDFGRTR2_EL2_nPMSSCR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
332
#define HDFGRTR2_EL2_nPMSSCR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
334
#define HDFGRTR2_EL2_nPMSSDATA_MASK (UL(0x1) << HDFGRTR2_EL2_nPMSSDATA_SHIFT)
sys/arm64/include/hypervisor.h
336
#define HDFGRTR2_EL2_nPMSSDATA_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMSSDATA_SHIFT)
sys/arm64/include/hypervisor.h
337
#define HDFGRTR2_EL2_nPMSSDATA_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMSSDATA_SHIFT)
sys/arm64/include/hypervisor.h
339
#define HDFGRTR2_EL2_nMDSELR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
341
#define HDFGRTR2_EL2_nMDSELR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
342
#define HDFGRTR2_EL2_nMDSELR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nMDSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
344
#define HDFGRTR2_EL2_nPMUACR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
346
#define HDFGRTR2_EL2_nPMUACR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
347
#define HDFGRTR2_EL2_nPMUACR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMUACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
349
#define HDFGRTR2_EL2_nPMICFILTR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
351
#define HDFGRTR2_EL2_nPMICFILTR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
352
#define HDFGRTR2_EL2_nPMICFILTR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMICFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
354
#define HDFGRTR2_EL2_nPMICNTR_EL0_MASK (UL(0x1) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
356
#define HDFGRTR2_EL2_nPMICNTR_EL0_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
357
#define HDFGRTR2_EL2_nPMICNTR_EL0_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMICNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
359
#define HDFGRTR2_EL2_nPMIAR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
361
#define HDFGRTR2_EL2_nPMIAR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
362
#define HDFGRTR2_EL2_nPMIAR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMIAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
364
#define HDFGRTR2_EL2_nPMECR_EL1_MASK (UL(0x1) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
366
#define HDFGRTR2_EL2_nPMECR_EL1_TRAP (UL(0x0) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
367
#define HDFGRTR2_EL2_nPMECR_EL1_NOTRAP (UL(0x1) << HDFGRTR2_EL2_nPMECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
377
#define HDFGRTR_EL2_PMBIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
379
#define HDFGRTR_EL2_PMBIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
380
#define HDFGRTR_EL2_PMBIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
382
#define HDFGRTR_EL2_nPMSNEVFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
384
#define HDFGRTR_EL2_nPMSNEVFR_EL1_TRAP (UL(0x0) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
385
#define HDFGRTR_EL2_nPMSNEVFR_EL1_NOTRAP (UL(0x1) << HDFGRTR_EL2_nPMSNEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
387
#define HDFGRTR_EL2_nBRBDATA_MASK (UL(0x1) << HDFGRTR_EL2_nBRBDATA_SHIFT)
sys/arm64/include/hypervisor.h
389
#define HDFGRTR_EL2_nBRBDATA_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBDATA_SHIFT)
sys/arm64/include/hypervisor.h
390
#define HDFGRTR_EL2_nBRBDATA_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBDATA_SHIFT)
sys/arm64/include/hypervisor.h
392
#define HDFGRTR_EL2_nBRBCTL_MASK (UL(0x1) << HDFGRTR_EL2_nBRBCTL_SHIFT)
sys/arm64/include/hypervisor.h
394
#define HDFGRTR_EL2_nBRBCTL_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBCTL_SHIFT)
sys/arm64/include/hypervisor.h
395
#define HDFGRTR_EL2_nBRBCTL_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBCTL_SHIFT)
sys/arm64/include/hypervisor.h
397
#define HDFGRTR_EL2_nBRBIDR_MASK (UL(0x1) << HDFGRTR_EL2_nBRBIDR_SHIFT)
sys/arm64/include/hypervisor.h
399
#define HDFGRTR_EL2_nBRBIDR_TRAP (UL(0x0) << HDFGRTR_EL2_nBRBIDR_SHIFT)
sys/arm64/include/hypervisor.h
400
#define HDFGRTR_EL2_nBRBIDR_NOTRAP (UL(0x1) << HDFGRTR_EL2_nBRBIDR_SHIFT)
sys/arm64/include/hypervisor.h
402
#define HDFGRTR_EL2_PMCEIDn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
404
#define HDFGRTR_EL2_PMCEIDn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
405
#define HDFGRTR_EL2_PMCEIDn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCEIDn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
407
#define HDFGRTR_EL2_PMUSERENR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
409
#define HDFGRTR_EL2_PMUSERENR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
410
#define HDFGRTR_EL2_PMUSERENR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMUSERENR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
412
#define HDFGRTR_EL2_TRBTRG_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT)
sys/arm64/include/hypervisor.h
414
#define HDFGRTR_EL2_TRBTRG_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT)
sys/arm64/include/hypervisor.h
415
#define HDFGRTR_EL2_TRBTRG_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBTRG_EL1_SHIFT)
sys/arm64/include/hypervisor.h
417
#define HDFGRTR_EL2_TRBSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
419
#define HDFGRTR_EL2_TRBSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
420
#define HDFGRTR_EL2_TRBSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
422
#define HDFGRTR_EL2_TRBPTR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
424
#define HDFGRTR_EL2_TRBPTR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
425
#define HDFGRTR_EL2_TRBPTR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
427
#define HDFGRTR_EL2_TRBMAR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
429
#define HDFGRTR_EL2_TRBMAR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
430
#define HDFGRTR_EL2_TRBMAR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBMAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
432
#define HDFGRTR_EL2_TRBLIMITR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
434
#define HDFGRTR_EL2_TRBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
435
#define HDFGRTR_EL2_TRBLIMITR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
437
#define HDFGRTR_EL2_TRBIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
439
#define HDFGRTR_EL2_TRBIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
440
#define HDFGRTR_EL2_TRBIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
442
#define HDFGRTR_EL2_TRBBASER_EL1_MASK (UL(0x1) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT)
sys/arm64/include/hypervisor.h
444
#define HDFGRTR_EL2_TRBBASER_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT)
sys/arm64/include/hypervisor.h
445
#define HDFGRTR_EL2_TRBBASER_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_TRBBASER_EL1_SHIFT)
sys/arm64/include/hypervisor.h
447
#define HDFGRTR_EL2_TRCVICTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCVICTLR_SHIFT)
sys/arm64/include/hypervisor.h
449
#define HDFGRTR_EL2_TRCVICTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCVICTLR_SHIFT)
sys/arm64/include/hypervisor.h
450
#define HDFGRTR_EL2_TRCVICTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCVICTLR_SHIFT)
sys/arm64/include/hypervisor.h
452
#define HDFGRTR_EL2_TRCSTATR_MASK (UL(0x1) << HDFGRTR_EL2_TRCSTATR_SHIFT)
sys/arm64/include/hypervisor.h
454
#define HDFGRTR_EL2_TRCSTATR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSTATR_SHIFT)
sys/arm64/include/hypervisor.h
455
#define HDFGRTR_EL2_TRCSTATR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSTATR_SHIFT)
sys/arm64/include/hypervisor.h
457
#define HDFGRTR_EL2_TRCSSCSRn_MASK (UL(0x1) << HDFGRTR_EL2_TRCSSCSRn_SHIFT)
sys/arm64/include/hypervisor.h
459
#define HDFGRTR_EL2_TRCSSCSRn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSSCSRn_SHIFT)
sys/arm64/include/hypervisor.h
460
#define HDFGRTR_EL2_TRCSSCSRn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSSCSRn_SHIFT)
sys/arm64/include/hypervisor.h
462
#define HDFGRTR_EL2_TRCSEQSTR_MASK (UL(0x1) << HDFGRTR_EL2_TRCSEQSTR_SHIFT)
sys/arm64/include/hypervisor.h
464
#define HDFGRTR_EL2_TRCSEQSTR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCSEQSTR_SHIFT)
sys/arm64/include/hypervisor.h
465
#define HDFGRTR_EL2_TRCSEQSTR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCSEQSTR_SHIFT)
sys/arm64/include/hypervisor.h
467
#define HDFGRTR_EL2_TRCPRGCTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT)
sys/arm64/include/hypervisor.h
469
#define HDFGRTR_EL2_TRCPRGCTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT)
sys/arm64/include/hypervisor.h
470
#define HDFGRTR_EL2_TRCPRGCTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCPRGCTLR_SHIFT)
sys/arm64/include/hypervisor.h
472
#define HDFGRTR_EL2_TRCOSLSR_MASK (UL(0x1) << HDFGRTR_EL2_TRCOSLSR_SHIFT)
sys/arm64/include/hypervisor.h
474
#define HDFGRTR_EL2_TRCOSLSR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCOSLSR_SHIFT)
sys/arm64/include/hypervisor.h
475
#define HDFGRTR_EL2_TRCOSLSR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCOSLSR_SHIFT)
sys/arm64/include/hypervisor.h
477
#define HDFGRTR_EL2_TRCIMSPECn_MASK (UL(0x1) << HDFGRTR_EL2_TRCIMSPECn_SHIFT)
sys/arm64/include/hypervisor.h
479
#define HDFGRTR_EL2_TRCIMSPECn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCIMSPECn_SHIFT)
sys/arm64/include/hypervisor.h
480
#define HDFGRTR_EL2_TRCIMSPECn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCIMSPECn_SHIFT)
sys/arm64/include/hypervisor.h
482
#define HDFGRTR_EL2_TRCID_MASK (UL(0x1) << HDFGRTR_EL2_TRCID_SHIFT)
sys/arm64/include/hypervisor.h
484
#define HDFGRTR_EL2_TRCID_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCID_SHIFT)
sys/arm64/include/hypervisor.h
485
#define HDFGRTR_EL2_TRCID_TRAP (UL(0x1) << HDFGRTR_EL2_TRCID_SHIFT)
sys/arm64/include/hypervisor.h
487
#define HDFGRTR_EL2_TRCCNTVRn_MASK (UL(0x1) << HDFGRTR_EL2_TRCCNTVRn_SHIFT)
sys/arm64/include/hypervisor.h
489
#define HDFGRTR_EL2_TRCCNTVRn_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCCNTVRn_SHIFT)
sys/arm64/include/hypervisor.h
490
#define HDFGRTR_EL2_TRCCNTVRn_TRAP (UL(0x1) << HDFGRTR_EL2_TRCCNTVRn_SHIFT)
sys/arm64/include/hypervisor.h
492
#define HDFGRTR_EL2_TRCCLAIM_MASK (UL(0x1) << HDFGRTR_EL2_TRCCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
494
#define HDFGRTR_EL2_TRCCLAIM_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
495
#define HDFGRTR_EL2_TRCCLAIM_TRAP (UL(0x1) << HDFGRTR_EL2_TRCCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
497
#define HDFGRTR_EL2_TRCAUXCTLR_MASK (UL(0x1) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT)
sys/arm64/include/hypervisor.h
499
#define HDFGRTR_EL2_TRCAUXCTLR_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT)
sys/arm64/include/hypervisor.h
500
#define HDFGRTR_EL2_TRCAUXCTLR_TRAP (UL(0x1) << HDFGRTR_EL2_TRCAUXCTLR_SHIFT)
sys/arm64/include/hypervisor.h
502
#define HDFGRTR_EL2_TRCAUTHSTATUS_MASK (UL(0x1) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT)
sys/arm64/include/hypervisor.h
504
#define HDFGRTR_EL2_TRCAUTHSTATUS_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT)
sys/arm64/include/hypervisor.h
505
#define HDFGRTR_EL2_TRCAUTHSTATUS_TRAP (UL(0x1) << HDFGRTR_EL2_TRCAUTHSTATUS_SHIFT)
sys/arm64/include/hypervisor.h
507
#define HDFGRTR_EL2_TRC_MASK (UL(0x1) << HDFGRTR_EL2_TRC_SHIFT)
sys/arm64/include/hypervisor.h
509
#define HDFGRTR_EL2_TRC_NOTRAP (UL(0x0) << HDFGRTR_EL2_TRC_SHIFT)
sys/arm64/include/hypervisor.h
510
#define HDFGRTR_EL2_TRC_TRAP (UL(0x1) << HDFGRTR_EL2_TRC_SHIFT)
sys/arm64/include/hypervisor.h
512
#define HDFGRTR_EL2_PMSLATFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
514
#define HDFGRTR_EL2_PMSLATFR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
515
#define HDFGRTR_EL2_PMSLATFR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSLATFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
517
#define HDFGRTR_EL2_PMSIRR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
519
#define HDFGRTR_EL2_PMSIRR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
520
#define HDFGRTR_EL2_PMSIRR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSIRR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
522
#define HDFGRTR_EL2_PMSIDR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
524
#define HDFGRTR_EL2_PMSIDR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
525
#define HDFGRTR_EL2_PMSIDR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSIDR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
527
#define HDFGRTR_EL2_PMSICR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSICR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
529
#define HDFGRTR_EL2_PMSICR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSICR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
530
#define HDFGRTR_EL2_PMSICR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSICR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
532
#define HDFGRTR_EL2_PMSFCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
534
#define HDFGRTR_EL2_PMSFCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
535
#define HDFGRTR_EL2_PMSFCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
537
#define HDFGRTR_EL2_PMSEVFR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
539
#define HDFGRTR_EL2_PMSEVFR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
540
#define HDFGRTR_EL2_PMSEVFR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
542
#define HDFGRTR_EL2_PMSCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
544
#define HDFGRTR_EL2_PMSCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
545
#define HDFGRTR_EL2_PMSCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
547
#define HDFGRTR_EL2_PMBSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
549
#define HDFGRTR_EL2_PMBSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
550
#define HDFGRTR_EL2_PMBSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
552
#define HDFGRTR_EL2_PMBPTR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
554
#define HDFGRTR_EL2_PMBPTR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
555
#define HDFGRTR_EL2_PMBPTR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
557
#define HDFGRTR_EL2_PMBLIMITR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
559
#define HDFGRTR_EL2_PMBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
560
#define HDFGRTR_EL2_PMBLIMITR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
562
#define HDFGRTR_EL2_PMMIR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_PMMIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
564
#define HDFGRTR_EL2_PMMIR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMMIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
565
#define HDFGRTR_EL2_PMMIR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_PMMIR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
567
#define HDFGRTR_EL2_PMSELR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
569
#define HDFGRTR_EL2_PMSELR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
570
#define HDFGRTR_EL2_PMSELR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
572
#define HDFGRTR_EL2_PMOVS_MASK (UL(0x1) << HDFGRTR_EL2_PMOVS_SHIFT)
sys/arm64/include/hypervisor.h
574
#define HDFGRTR_EL2_PMOVS_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMOVS_SHIFT)
sys/arm64/include/hypervisor.h
575
#define HDFGRTR_EL2_PMOVS_TRAP (UL(0x1) << HDFGRTR_EL2_PMOVS_SHIFT)
sys/arm64/include/hypervisor.h
577
#define HDFGRTR_EL2_PMINTEN_MASK (UL(0x1) << HDFGRTR_EL2_PMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
579
#define HDFGRTR_EL2_PMINTEN_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
580
#define HDFGRTR_EL2_PMINTEN_TRAP (UL(0x1) << HDFGRTR_EL2_PMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
582
#define HDFGRTR_EL2_PMCNTEN_MASK (UL(0x1) << HDFGRTR_EL2_PMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
584
#define HDFGRTR_EL2_PMCNTEN_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
585
#define HDFGRTR_EL2_PMCNTEN_TRAP (UL(0x1) << HDFGRTR_EL2_PMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
587
#define HDFGRTR_EL2_PMCCNTR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
589
#define HDFGRTR_EL2_PMCCNTR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
590
#define HDFGRTR_EL2_PMCCNTR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCCNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
592
#define HDFGRTR_EL2_PMCCFILTR_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
594
#define HDFGRTR_EL2_PMCCFILTR_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
595
#define HDFGRTR_EL2_PMCCFILTR_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMCCFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
597
#define HDFGRTR_EL2_PMEVTYPERn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
599
#define HDFGRTR_EL2_PMEVTYPERn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
600
#define HDFGRTR_EL2_PMEVTYPERn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
602
#define HDFGRTR_EL2_PMEVCNTRn_EL0_MASK (UL(0x1) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
604
#define HDFGRTR_EL2_PMEVCNTRn_EL0_NOTRAP (UL(0x0) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
605
#define HDFGRTR_EL2_PMEVCNTRn_EL0_TRAP (UL(0x1) << HDFGRTR_EL2_PMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
607
#define HDFGRTR_EL2_OSDLR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSDLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
609
#define HDFGRTR_EL2_OSDLR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSDLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
610
#define HDFGRTR_EL2_OSDLR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSDLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
612
#define HDFGRTR_EL2_OSECCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSECCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
614
#define HDFGRTR_EL2_OSECCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSECCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
615
#define HDFGRTR_EL2_OSECCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSECCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
617
#define HDFGRTR_EL2_OSLSR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_OSLSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
619
#define HDFGRTR_EL2_OSLSR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_OSLSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
620
#define HDFGRTR_EL2_OSLSR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_OSLSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
622
#define HDFGRTR_EL2_DBGPRCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
624
#define HDFGRTR_EL2_DBGPRCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
625
#define HDFGRTR_EL2_DBGPRCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGPRCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
627
#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
629
#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
630
#define HDFGRTR_EL2_DBGAUTHSTATUS_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGAUTHSTATUS_EL1_SHIFT)
sys/arm64/include/hypervisor.h
632
#define HDFGRTR_EL2_DBGCLAIM_MASK (UL(0x1) << HDFGRTR_EL2_DBGCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
634
#define HDFGRTR_EL2_DBGCLAIM_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
635
#define HDFGRTR_EL2_DBGCLAIM_TRAP (UL(0x1) << HDFGRTR_EL2_DBGCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
637
#define HDFGRTR_EL2_MDSCR_EL1_MASK (UL(0x1) << HDFGRTR_EL2_MDSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
639
#define HDFGRTR_EL2_MDSCR_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_MDSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
640
#define HDFGRTR_EL2_MDSCR_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_MDSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
642
#define HDFGRTR_EL2_DBGWVRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
644
#define HDFGRTR_EL2_DBGWVRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
645
#define HDFGRTR_EL2_DBGWVRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGWVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
647
#define HDFGRTR_EL2_DBGWCRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
649
#define HDFGRTR_EL2_DBGWCRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
650
#define HDFGRTR_EL2_DBGWCRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGWCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
652
#define HDFGRTR_EL2_DBGBVRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
654
#define HDFGRTR_EL2_DBGBVRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
655
#define HDFGRTR_EL2_DBGBVRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGBVRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
657
#define HDFGRTR_EL2_DBGBCRn_EL1_MASK (UL(0x1) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
659
#define HDFGRTR_EL2_DBGBCRn_EL1_NOTRAP (UL(0x0) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
660
#define HDFGRTR_EL2_DBGBCRn_EL1_TRAP (UL(0x1) << HDFGRTR_EL2_DBGBCRn_EL1_SHIFT)
sys/arm64/include/hypervisor.h
670
#define HDFGWTR2_EL2_nMDSTEPOP_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT)
sys/arm64/include/hypervisor.h
672
#define HDFGWTR2_EL2_nMDSTEPOP_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT)
sys/arm64/include/hypervisor.h
673
#define HDFGWTR2_EL2_nMDSTEPOP_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nMDSTEPOP_EL1_SHIFT)
sys/arm64/include/hypervisor.h
675
#define HDFGWTR2_EL2_nTRBMPAM_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
677
#define HDFGWTR2_EL2_nTRBMPAM_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
678
#define HDFGWTR2_EL2_nTRBMPAM_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nTRBMPAM_EL1_SHIFT)
sys/arm64/include/hypervisor.h
680
#define HDFGWTR2_EL2_nPMZR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
682
#define HDFGWTR2_EL2_nPMZR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
683
#define HDFGWTR2_EL2_nPMZR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMZR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
685
#define HDFGWTR2_EL2_nTRCITECR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
687
#define HDFGWTR2_EL2_nTRCITECR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
688
#define HDFGWTR2_EL2_nTRCITECR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nTRCITECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
690
#define HDFGWTR2_EL2_nPMSDSFR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
692
#define HDFGWTR2_EL2_nPMSDSFR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
693
#define HDFGWTR2_EL2_nPMSDSFR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMSDSFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
695
#define HDFGWTR2_EL2_nSPMSCR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
697
#define HDFGWTR2_EL2_nSPMSCR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
698
#define HDFGWTR2_EL2_nSPMSCR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
700
#define HDFGWTR2_EL2_nSPMACCESSR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
702
#define HDFGWTR2_EL2_nSPMACCESSR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
703
#define HDFGWTR2_EL2_nSPMACCESSR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMACCESSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
705
#define HDFGWTR2_EL2_nSPMCR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
707
#define HDFGWTR2_EL2_nSPMCR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
708
#define HDFGWTR2_EL2_nSPMCR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
710
#define HDFGWTR2_EL2_nSPMOVS_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMOVS_SHIFT)
sys/arm64/include/hypervisor.h
712
#define HDFGWTR2_EL2_nSPMOVS_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMOVS_SHIFT)
sys/arm64/include/hypervisor.h
713
#define HDFGWTR2_EL2_nSPMOVS_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMOVS_SHIFT)
sys/arm64/include/hypervisor.h
715
#define HDFGWTR2_EL2_nSPMINTEN_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
717
#define HDFGWTR2_EL2_nSPMINTEN_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
718
#define HDFGWTR2_EL2_nSPMINTEN_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
720
#define HDFGWTR2_EL2_nSPMCNTEN_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
722
#define HDFGWTR2_EL2_nSPMCNTEN_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
723
#define HDFGWTR2_EL2_nSPMCNTEN_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
725
#define HDFGWTR2_EL2_nSPMSELR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
727
#define HDFGWTR2_EL2_nSPMSELR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
728
#define HDFGWTR2_EL2_nSPMSELR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
730
#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
732
#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
733
#define HDFGWTR2_EL2_nSPMEVTYPERn_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
735
#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
737
#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
738
#define HDFGWTR2_EL2_nSPMEVCNTRn_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nSPMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
740
#define HDFGWTR2_EL2_nPMSSCR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
742
#define HDFGWTR2_EL2_nPMSSCR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
743
#define HDFGWTR2_EL2_nPMSSCR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMSSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
745
#define HDFGWTR2_EL2_nMDSELR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
747
#define HDFGWTR2_EL2_nMDSELR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
748
#define HDFGWTR2_EL2_nMDSELR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nMDSELR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
750
#define HDFGWTR2_EL2_nPMUACR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
752
#define HDFGWTR2_EL2_nPMUACR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
753
#define HDFGWTR2_EL2_nPMUACR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMUACR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
755
#define HDFGWTR2_EL2_nPMICFILTR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
757
#define HDFGWTR2_EL2_nPMICFILTR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
758
#define HDFGWTR2_EL2_nPMICFILTR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMICFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
760
#define HDFGWTR2_EL2_nPMICNTR_EL0_MASK (UL(0x1) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
762
#define HDFGWTR2_EL2_nPMICNTR_EL0_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
763
#define HDFGWTR2_EL2_nPMICNTR_EL0_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMICNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
765
#define HDFGWTR2_EL2_nPMIAR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
767
#define HDFGWTR2_EL2_nPMIAR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
768
#define HDFGWTR2_EL2_nPMIAR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMIAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
770
#define HDFGWTR2_EL2_nPMECR_EL1_MASK (UL(0x1) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
772
#define HDFGWTR2_EL2_nPMECR_EL1_TRAP (UL(0x0) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
773
#define HDFGWTR2_EL2_nPMECR_EL1_NOTRAP (UL(0x1) << HDFGWTR2_EL2_nPMECR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
783
#define HDFGWTR_EL2_nPMSNEVFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
785
#define HDFGWTR_EL2_nPMSNEVFR_EL1_TRAP (UL(0x0) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
786
#define HDFGWTR_EL2_nPMSNEVFR_EL1_NOTRAP (UL(0x1) << HDFGWTR_EL2_nPMSNEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
788
#define HDFGWTR_EL2_nBRBDATA_MASK (UL(0x1) << HDFGWTR_EL2_nBRBDATA_SHIFT)
sys/arm64/include/hypervisor.h
790
#define HDFGWTR_EL2_nBRBDATA_TRAP (UL(0x0) << HDFGWTR_EL2_nBRBDATA_SHIFT)
sys/arm64/include/hypervisor.h
791
#define HDFGWTR_EL2_nBRBDATA_NOTRAP (UL(0x1) << HDFGWTR_EL2_nBRBDATA_SHIFT)
sys/arm64/include/hypervisor.h
793
#define HDFGWTR_EL2_nBRBCTL_MASK (UL(0x1) << HDFGWTR_EL2_nBRBCTL_SHIFT)
sys/arm64/include/hypervisor.h
795
#define HDFGWTR_EL2_nBRBCTL_TRAP (UL(0x0) << HDFGWTR_EL2_nBRBCTL_SHIFT)
sys/arm64/include/hypervisor.h
796
#define HDFGWTR_EL2_nBRBCTL_NOTRAP (UL(0x1) << HDFGWTR_EL2_nBRBCTL_SHIFT)
sys/arm64/include/hypervisor.h
798
#define HDFGWTR_EL2_PMUSERENR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
800
#define HDFGWTR_EL2_PMUSERENR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
801
#define HDFGWTR_EL2_PMUSERENR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMUSERENR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
803
#define HDFGWTR_EL2_TRBTRG_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT)
sys/arm64/include/hypervisor.h
805
#define HDFGWTR_EL2_TRBTRG_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT)
sys/arm64/include/hypervisor.h
806
#define HDFGWTR_EL2_TRBTRG_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBTRG_EL1_SHIFT)
sys/arm64/include/hypervisor.h
808
#define HDFGWTR_EL2_TRBSR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
810
#define HDFGWTR_EL2_TRBSR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
811
#define HDFGWTR_EL2_TRBSR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
813
#define HDFGWTR_EL2_TRBPTR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
815
#define HDFGWTR_EL2_TRBPTR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
816
#define HDFGWTR_EL2_TRBPTR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
818
#define HDFGWTR_EL2_TRBMAR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
820
#define HDFGWTR_EL2_TRBMAR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
821
#define HDFGWTR_EL2_TRBMAR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBMAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
823
#define HDFGWTR_EL2_TRBLIMITR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
825
#define HDFGWTR_EL2_TRBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
826
#define HDFGWTR_EL2_TRBLIMITR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
828
#define HDFGWTR_EL2_TRBBASER_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT)
sys/arm64/include/hypervisor.h
830
#define HDFGWTR_EL2_TRBBASER_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT)
sys/arm64/include/hypervisor.h
831
#define HDFGWTR_EL2_TRBBASER_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRBBASER_EL1_SHIFT)
sys/arm64/include/hypervisor.h
833
#define HDFGWTR_EL2_TRFCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_TRFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
835
#define HDFGWTR_EL2_TRFCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
836
#define HDFGWTR_EL2_TRFCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_TRFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
838
#define HDFGWTR_EL2_TRCVICTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCVICTLR_SHIFT)
sys/arm64/include/hypervisor.h
840
#define HDFGWTR_EL2_TRCVICTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCVICTLR_SHIFT)
sys/arm64/include/hypervisor.h
841
#define HDFGWTR_EL2_TRCVICTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCVICTLR_SHIFT)
sys/arm64/include/hypervisor.h
843
#define HDFGWTR_EL2_TRCSSCSRn_MASK (UL(0x1) << HDFGWTR_EL2_TRCSSCSRn_SHIFT)
sys/arm64/include/hypervisor.h
845
#define HDFGWTR_EL2_TRCSSCSRn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCSSCSRn_SHIFT)
sys/arm64/include/hypervisor.h
846
#define HDFGWTR_EL2_TRCSSCSRn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCSSCSRn_SHIFT)
sys/arm64/include/hypervisor.h
848
#define HDFGWTR_EL2_TRCSEQSTR_MASK (UL(0x1) << HDFGWTR_EL2_TRCSEQSTR_SHIFT)
sys/arm64/include/hypervisor.h
850
#define HDFGWTR_EL2_TRCSEQSTR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCSEQSTR_SHIFT)
sys/arm64/include/hypervisor.h
851
#define HDFGWTR_EL2_TRCSEQSTR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCSEQSTR_SHIFT)
sys/arm64/include/hypervisor.h
853
#define HDFGWTR_EL2_TRCPRGCTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT)
sys/arm64/include/hypervisor.h
855
#define HDFGWTR_EL2_TRCPRGCTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT)
sys/arm64/include/hypervisor.h
856
#define HDFGWTR_EL2_TRCPRGCTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCPRGCTLR_SHIFT)
sys/arm64/include/hypervisor.h
858
#define HDFGWTR_EL2_TRCOSLAR_MASK (UL(0x1) << HDFGWTR_EL2_TRCOSLAR_SHIFT)
sys/arm64/include/hypervisor.h
860
#define HDFGWTR_EL2_TRCOSLAR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCOSLAR_SHIFT)
sys/arm64/include/hypervisor.h
861
#define HDFGWTR_EL2_TRCOSLAR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCOSLAR_SHIFT)
sys/arm64/include/hypervisor.h
863
#define HDFGWTR_EL2_TRCIMSPECn_MASK (UL(0x1) << HDFGWTR_EL2_TRCIMSPECn_SHIFT)
sys/arm64/include/hypervisor.h
865
#define HDFGWTR_EL2_TRCIMSPECn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCIMSPECn_SHIFT)
sys/arm64/include/hypervisor.h
866
#define HDFGWTR_EL2_TRCIMSPECn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCIMSPECn_SHIFT)
sys/arm64/include/hypervisor.h
868
#define HDFGWTR_EL2_TRCCNTVRn_MASK (UL(0x1) << HDFGWTR_EL2_TRCCNTVRn_SHIFT)
sys/arm64/include/hypervisor.h
870
#define HDFGWTR_EL2_TRCCNTVRn_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCCNTVRn_SHIFT)
sys/arm64/include/hypervisor.h
871
#define HDFGWTR_EL2_TRCCNTVRn_TRAP (UL(0x1) << HDFGWTR_EL2_TRCCNTVRn_SHIFT)
sys/arm64/include/hypervisor.h
873
#define HDFGWTR_EL2_TRCCLAIM_MASK (UL(0x1) << HDFGWTR_EL2_TRCCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
875
#define HDFGWTR_EL2_TRCCLAIM_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
876
#define HDFGWTR_EL2_TRCCLAIM_TRAP (UL(0x1) << HDFGWTR_EL2_TRCCLAIM_SHIFT)
sys/arm64/include/hypervisor.h
878
#define HDFGWTR_EL2_TRCAUXCTLR_MASK (UL(0x1) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT)
sys/arm64/include/hypervisor.h
880
#define HDFGWTR_EL2_TRCAUXCTLR_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT)
sys/arm64/include/hypervisor.h
881
#define HDFGWTR_EL2_TRCAUXCTLR_TRAP (UL(0x1) << HDFGWTR_EL2_TRCAUXCTLR_SHIFT)
sys/arm64/include/hypervisor.h
883
#define HDFGWTR_EL2_TRC_MASK (UL(0x1) << HDFGWTR_EL2_TRC_SHIFT)
sys/arm64/include/hypervisor.h
885
#define HDFGWTR_EL2_TRC_NOTRAP (UL(0x0) << HDFGWTR_EL2_TRC_SHIFT)
sys/arm64/include/hypervisor.h
886
#define HDFGWTR_EL2_TRC_TRAP (UL(0x1) << HDFGWTR_EL2_TRC_SHIFT)
sys/arm64/include/hypervisor.h
888
#define HDFGWTR_EL2_PMSLATFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
890
#define HDFGWTR_EL2_PMSLATFR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
891
#define HDFGWTR_EL2_PMSLATFR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSLATFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
893
#define HDFGWTR_EL2_PMSIRR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
895
#define HDFGWTR_EL2_PMSIRR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
896
#define HDFGWTR_EL2_PMSIRR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSIRR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
898
#define HDFGWTR_EL2_PMSICR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSICR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
900
#define HDFGWTR_EL2_PMSICR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSICR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
901
#define HDFGWTR_EL2_PMSICR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSICR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
903
#define HDFGWTR_EL2_PMSFCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
905
#define HDFGWTR_EL2_PMSFCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
906
#define HDFGWTR_EL2_PMSFCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSFCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
908
#define HDFGWTR_EL2_PMSEVFR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
910
#define HDFGWTR_EL2_PMSEVFR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
911
#define HDFGWTR_EL2_PMSEVFR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSEVFR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
913
#define HDFGWTR_EL2_PMSCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
915
#define HDFGWTR_EL2_PMSCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
916
#define HDFGWTR_EL2_PMSCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMSCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
918
#define HDFGWTR_EL2_PMBSR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
920
#define HDFGWTR_EL2_PMBSR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
921
#define HDFGWTR_EL2_PMBSR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBSR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
923
#define HDFGWTR_EL2_PMBPTR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
925
#define HDFGWTR_EL2_PMBPTR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
926
#define HDFGWTR_EL2_PMBPTR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBPTR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
928
#define HDFGWTR_EL2_PMBLIMITR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
930
#define HDFGWTR_EL2_PMBLIMITR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
931
#define HDFGWTR_EL2_PMBLIMITR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_PMBLIMITR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
933
#define HDFGWTR_EL2_PMCR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
935
#define HDFGWTR_EL2_PMCR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
936
#define HDFGWTR_EL2_PMCR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
938
#define HDFGWTR_EL2_PMSWINC_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT)
sys/arm64/include/hypervisor.h
940
#define HDFGWTR_EL2_PMSWINC_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT)
sys/arm64/include/hypervisor.h
941
#define HDFGWTR_EL2_PMSWINC_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMSWINC_EL0_SHIFT)
sys/arm64/include/hypervisor.h
943
#define HDFGWTR_EL2_PMSELR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
945
#define HDFGWTR_EL2_PMSELR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
946
#define HDFGWTR_EL2_PMSELR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMSELR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
948
#define HDFGWTR_EL2_PMOVS_MASK (UL(0x1) << HDFGWTR_EL2_PMOVS_SHIFT)
sys/arm64/include/hypervisor.h
950
#define HDFGWTR_EL2_PMOVS_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMOVS_SHIFT)
sys/arm64/include/hypervisor.h
951
#define HDFGWTR_EL2_PMOVS_TRAP (UL(0x1) << HDFGWTR_EL2_PMOVS_SHIFT)
sys/arm64/include/hypervisor.h
953
#define HDFGWTR_EL2_PMINTEN_MASK (UL(0x1) << HDFGWTR_EL2_PMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
955
#define HDFGWTR_EL2_PMINTEN_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
956
#define HDFGWTR_EL2_PMINTEN_TRAP (UL(0x1) << HDFGWTR_EL2_PMINTEN_SHIFT)
sys/arm64/include/hypervisor.h
958
#define HDFGWTR_EL2_PMCNTEN_MASK (UL(0x1) << HDFGWTR_EL2_PMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
960
#define HDFGWTR_EL2_PMCNTEN_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
961
#define HDFGWTR_EL2_PMCNTEN_TRAP (UL(0x1) << HDFGWTR_EL2_PMCNTEN_SHIFT)
sys/arm64/include/hypervisor.h
963
#define HDFGWTR_EL2_PMCCNTR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
965
#define HDFGWTR_EL2_PMCCNTR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
966
#define HDFGWTR_EL2_PMCCNTR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCCNTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
968
#define HDFGWTR_EL2_PMCCFILTR_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
970
#define HDFGWTR_EL2_PMCCFILTR_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
971
#define HDFGWTR_EL2_PMCCFILTR_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMCCFILTR_EL0_SHIFT)
sys/arm64/include/hypervisor.h
973
#define HDFGWTR_EL2_PMEVTYPERn_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
975
#define HDFGWTR_EL2_PMEVTYPERn_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
976
#define HDFGWTR_EL2_PMEVTYPERn_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMEVTYPERn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
978
#define HDFGWTR_EL2_PMEVCNTRn_EL0_MASK (UL(0x1) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
980
#define HDFGWTR_EL2_PMEVCNTRn_EL0_NOTRAP (UL(0x0) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
981
#define HDFGWTR_EL2_PMEVCNTRn_EL0_TRAP (UL(0x1) << HDFGWTR_EL2_PMEVCNTRn_EL0_SHIFT)
sys/arm64/include/hypervisor.h
983
#define HDFGWTR_EL2_OSDLR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSDLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
985
#define HDFGWTR_EL2_OSDLR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSDLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
986
#define HDFGWTR_EL2_OSDLR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSDLR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
988
#define HDFGWTR_EL2_OSECCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSECCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
990
#define HDFGWTR_EL2_OSECCR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSECCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
991
#define HDFGWTR_EL2_OSECCR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSECCR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
993
#define HDFGWTR_EL2_OSLAR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_OSLAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
995
#define HDFGWTR_EL2_OSLAR_EL1_NOTRAP (UL(0x0) << HDFGWTR_EL2_OSLAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
996
#define HDFGWTR_EL2_OSLAR_EL1_TRAP (UL(0x1) << HDFGWTR_EL2_OSLAR_EL1_SHIFT)
sys/arm64/include/hypervisor.h
998
#define HDFGWTR_EL2_DBGPRCR_EL1_MASK (UL(0x1) << HDFGWTR_EL2_DBGPRCR_EL1_SHIFT)
sys/arm64/spe/arm_spe_dev.c
74
#define ARM_SPE_KVA_MAX_ALIGN UL(2048)
sys/kern/kern_ubsan.c
1520
ulongest UL = 0;
sys/kern/kern_ubsan.c
1531
memcpy(&UL, REINTERPRET_CAST(ulongest *, ulNumber), sizeof(ulongest));
sys/kern/kern_ubsan.c
1539
UL = *REINTERPRET_CAST(uint64_t *, ulNumber);
sys/kern/kern_ubsan.c
1548
UL = ulNumber;
sys/kern/kern_ubsan.c
1552
return UL;
sys/kern/kern_ubsan.c
1607
ulongest UL = llluGetNumber(szLocation, pType, ulNumber);
sys/kern/kern_ubsan.c
1608
DeserializeNumberUnsigned(pBuffer, zBUfferLength, pType, UL);
sys/powerpc/include/_stdint.h
55
#define UINT64_C(c) (c ## UL)
sys/powerpc/include/_stdint.h
71
#define __UINT64_C(c) (c ## UL)
sys/riscv/include/_stdint.h
44
#define UINT64_C(c) (c ## UL)
sys/x86/include/_stdint.h
55
#define UINT64_C(c) (c ## UL)