sys/dev/tpm/tpm.c

394

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);

sys/dev/tpm/tpm.c

455

burst = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS + 1);

sys/dev/tpm/tpm.c

456

burst |= bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS + 2)

sys/dev/tpm/tpm.c

478

status = bus_space_read_1(sc->sc_bt, sc->sc_bh, TPM_STS) &

sys/dev/tpm/tpm.c

712

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,

sys/dev/tpm/tpm.c

752

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS, TPM_STS_CMD_READY);

sys/dev/tpm/tpm.c

889

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,

sys/dev/tpm/tpm.c

906

bus_space_write_1(sc->sc_bt, sc->sc_bh, TPM_STS,

sys/dev/tpm/tpm_tis_core.c

274

burst_count = (TPM_READ_4(sc->dev, TPM_STS) & TPM_STS_BURST_MASK) >>

sys/dev/tpm/tpm_tis_core.c

378

TPM_WRITE_4(sc->dev, TPM_STS, TPM_STS_CMD_RDY);

sys/dev/tpm/tpm_tis_core.c

379

TPM_WRITE_BARRIER(sc->dev, TPM_STS, 4);

sys/dev/tpm/tpm_tis_core.c

380

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_B))

sys/dev/tpm/tpm_tis_core.c

415

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C)) {

sys/dev/tpm/tpm_tis_core.c

420

if (TPM_READ_4(dev, TPM_STS) & TPM_STS_DATA_EXPECTED) {

sys/dev/tpm/tpm_tis_core.c

434

TPM_WRITE_4(dev, TPM_STS, TPM_STS_CMD_START);

sys/dev/tpm/tpm_tis_core.c

435

TPM_WRITE_BARRIER(dev, TPM_STS, 4);

sys/dev/tpm/tpm_tis_core.c

439

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, timeout)) {

sys/dev/tpm/tpm_tis_core.c

454

if (!tpm_wait_for_u32(sc, TPM_STS, mask, mask, TPM_TIMEOUT_C))

sys/dev/tpm/tpm_tis_core.c

485

TPM_WRITE_4(sc->dev, TPM_STS, TPM_STS_CMD_RDY);

sys/dev/tpm/tpm_tis_core.c

486

TPM_WRITE_BARRIER(sc->dev, TPM_STS, 4);