BMCR_RESET
MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
age_miibus_writereg(sc->age_dev, sc->age_phyaddr, MII_BMCR, BMCR_RESET);
BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
bfe_writephy(sc, 0, BMCR_RESET);
if (val & BMCR_RESET) {
sc->bge_phy_addr, MII_BMCR, BMCR_RESET);
v &= BMCR_RESET;
BMCR_RESET, BMCR_ANENABLE | BMCR_ANRESTART);
BMCR_RESET | BMCR_ANENABLE | BMCR_ANRESTART, 0);
v &= BMCR_RESET;
err = t3_mdio_change_bits(phy, mmd, MII_BMCR, BMCR_PDOWN, BMCR_RESET);
ctl &= BMCR_RESET;
PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN);
if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
reg = BMCR_RESET;
reg = BMCR_RESET | BMCR_ISO;
if ((reg & BMCR_RESET) == 0)
PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
reg = BMCR_RESET;
reg = BMCR_RESET | BMCR_ISO;
if (reg != 0 && (reg & BMCR_RESET) == 0)
reg = BMCR_RESET;
reg = BMCR_RESET | BMCR_ISO;
if (reg != 0 && (reg & BMCR_RESET) == 0)
PHY_WRITE(sc, MII_BMCR, BMCR_RESET);
if ((bmcr & BMCR_RESET) == 0)
if (bmcr & BMCR_RESET)
MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET);
if (!(status & BMCR_RESET))
rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
rge_write_phy(sc, 0, MII_BMCR, BMCR_RESET | BMCR_AUTOEN |
if (!(rge_read_phy(sc, 0, MII_BMCR) & BMCR_RESET))
BMCR_RESET);
} while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks));
smsc_miibus_writereg(sc->sc_ue.ue_dev, sc->sc_phyno, MII_BMCR, BMCR_RESET);
} while ((bmcr & BMCR_RESET) && ((ticks - start_ticks) < max_ticks));
BMCR_AUTOEN | BMCR_FDX | BMCR_SPEED1 | BMCR_RESET);