BIT_ULL
#define BIT_GAP(bits, end, start) ((((end) - (start)) + BIT_ULL(bits)) & (BIT_ULL(bits) - 1))
BSS_CHANGED_MLD_VALID_LINKS = BIT_ULL(32),
BSS_CHANGED_MLD_TTLM = BIT_ULL(33),
BSS_CHANGED_TPE = BIT_ULL(34),
if ((flags & BIT_ULL(bit)) == 0)
if ((sinfo.filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE)) == 0 &&
(lsta->sinfo.filled & BIT_ULL(NL80211_STA_INFO_RX_BITRATE)) != 0) {
sinfo.filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
if ((sinfo.filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) == 0 &&
(lsta->sinfo.filled & BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL)) != 0) {
sinfo.filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
lsta->sinfo.filled |= BIT_ULL(NL80211_STA_INFO_RX_BITRATE);
lsta->sinfo.filled |= BIT_ULL(NL80211_STA_INFO_CHAIN_SIGNAL);
#define BNXT_FW_CAP_SHORT_CMD BIT_ULL(0)
#define BNXT_FW_CAP_LLDP_AGENT BIT_ULL(1)
#define BNXT_FW_CAP_DCBX_AGENT BIT_ULL(2)
#define BNXT_FW_CAP_NEW_RM BIT_ULL(3)
#define BNXT_FW_CAP_IF_CHANGE BIT_ULL(4)
#define BNXT_FW_CAP_LINK_ADMIN BIT_ULL(5)
#define BNXT_FW_CAP_VF_RES_MIN_GUARANTEED BIT_ULL(6)
#define BNXT_FW_CAP_KONG_MB_CHNL BIT_ULL(7)
#define BNXT_FW_CAP_ADMIN_MTU BIT_ULL(8)
#define BNXT_FW_CAP_ADMIN_PF BIT_ULL(9)
#define BNXT_FW_CAP_OVS_64BIT_HANDLE BIT_ULL(10)
#define BNXT_FW_CAP_TRUSTED_VF BIT_ULL(11)
#define BNXT_FW_CAP_VF_VNIC_NOTIFY BIT_ULL(12)
#define BNXT_FW_CAP_ERROR_RECOVERY BIT_ULL(13)
#define BNXT_FW_CAP_PKG_VER BIT_ULL(14)
#define BNXT_FW_CAP_CFA_ADV_FLOW BIT_ULL(15)
#define BNXT_FW_CAP_CFA_RFS_RING_TBL_IDX_V2 BIT_ULL(16)
#define BNXT_FW_CAP_PCIE_STATS_SUPPORTED BIT_ULL(17)
#define BNXT_FW_CAP_EXT_STATS_SUPPORTED BIT_ULL(18)
#define BNXT_FW_CAP_SECURE_MODE BIT_ULL(19)
#define BNXT_FW_CAP_ERR_RECOVER_RELOAD BIT_ULL(20)
#define BNXT_FW_CAP_HOT_RESET BIT_ULL(21)
#define BNXT_FW_CAP_CRASHDUMP BIT_ULL(23)
#define BNXT_FW_CAP_VLAN_RX_STRIP BIT_ULL(24)
#define BNXT_FW_CAP_VLAN_TX_INSERT BIT_ULL(25)
#define BNXT_FW_CAP_EXT_HW_STATS_SUPPORTED BIT_ULL(26)
#define BNXT_FW_CAP_CFA_EEM BIT_ULL(27)
#define BNXT_FW_CAP_DBG_QCAPS BIT_ULL(29)
#define BNXT_FW_CAP_RING_MONITOR BIT_ULL(30)
#define BNXT_FW_CAP_ECN_STATS BIT_ULL(31)
#define BNXT_FW_CAP_TRUFLOW BIT_ULL(32)
#define BNXT_FW_CAP_VF_CFG_FOR_PF BIT_ULL(33)
#define BNXT_FW_CAP_PTP_PPS BIT_ULL(34)
#define BNXT_FW_CAP_HOT_RESET_IF BIT_ULL(35)
#define BNXT_FW_CAP_LIVEPATCH BIT_ULL(36)
#define BNXT_FW_CAP_NPAR_1_2 BIT_ULL(37)
#define BNXT_FW_CAP_RSS_HASH_TYPE_DELTA BIT_ULL(38)
#define BNXT_FW_CAP_PTP_RTC BIT_ULL(39)
#define BNXT_FW_CAP_TRUFLOW_EN BIT_ULL(40)
#define BNXT_FW_CAP_RX_ALL_PKT_TS BIT_ULL(41)
#define BNXT_FW_CAP_BACKING_STORE_V2 BIT_ULL(42)
#define BNXT_FW_CAP_DBR_SUPPORTED BIT_ULL(43)
#define BNXT_FW_CAP_GENERIC_STATS BIT_ULL(44)
#define BNXT_FW_CAP_DBR_PACING_SUPPORTED BIT_ULL(45)
#define BNXT_FW_CAP_PTP_PTM BIT_ULL(46)
#define BNXT_FW_CAP_CFA_NTUPLE_RX_EXT_IP_PROTO BIT_ULL(47)
#define BNXT_FW_CAP_ENABLE_RDMA_SRIOV BIT_ULL(48)
#define BNXT_FW_CAP_RSS_TCAM BIT_ULL(49)
#define BNXT_FW_CAP_SW_MAX_RESOURCE_LIMITS BIT_ULL(61)
#ifndef BIT_ULL
pmask = BIT_ULL(sginfo->pgshft) - 1;
BIT_ULL(hwq_attr->sginfo->pgshft);
BIT_ULL(hwq_attr->sginfo->pgshft))
attr->page_size_cap = BIT_ULL(28) | BIT_ULL(21) | BIT_ULL(12);
#define HV_HYPERCALL_REP_COMP_1 BIT_ULL(32)
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_TCP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
BIT_ULL(IAVF_FILTER_PCTYPE_FRAG_IPV4) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_TCP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
BIT_ULL(IAVF_FILTER_PCTYPE_FRAG_IPV6))
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
BIT_ULL(IAVF_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
BIT_ULL(IAVF_FILTER_PCTYPE_L2_PAYLOAD))
#define IAVF_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
#define IAVF_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
#define IAVF_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
#define IAVF_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
#define IAVF_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
#define IAVF_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(IAVF_RXD_QW1_STATUS_TSYNVALID_SHIFT)
#define IAVF_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(IAVF_RXD_QW1_LENGTH_SPH_SHIFT)
#define IAVF_TXD_FLTR_QW1_ATR_MASK BIT_ULL(IAVF_TXD_FLTR_QW1_ATR_SHIFT)
#define IAVF_TXD_CTX_UDP_TUNNELING BIT_ULL(IAVF_TXD_CTX_QW0_NATT_SHIFT)
BIT_ULL(IAVF_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define IAVF_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(IAVF_TXD_CTX_QW0_L4T_CS_SHIFT)
#define ICE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
#define ICE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
#define ICE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
#define ICE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
#define ICE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
#define ICE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
#define ICE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
#define ICE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
#define ICE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
#define ICE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
#define ICE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
#define ICE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
#define ICE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
#define ICE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
#define ICE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
#define ICE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
#define ICE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
#define ICE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
#define ICE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
#define ICE_PHY_TYPE_LOW_25GBASE_T BIT_ULL(19)
#define ICE_PHY_TYPE_LOW_25GBASE_CR BIT_ULL(20)
#define ICE_PHY_TYPE_LOW_25GBASE_CR_S BIT_ULL(21)
#define ICE_PHY_TYPE_LOW_25GBASE_CR1 BIT_ULL(22)
#define ICE_PHY_TYPE_LOW_25GBASE_SR BIT_ULL(23)
#define ICE_PHY_TYPE_LOW_25GBASE_LR BIT_ULL(24)
#define ICE_PHY_TYPE_LOW_25GBASE_KR BIT_ULL(25)
#define ICE_PHY_TYPE_LOW_25GBASE_KR_S BIT_ULL(26)
#define ICE_PHY_TYPE_LOW_25GBASE_KR1 BIT_ULL(27)
#define ICE_PHY_TYPE_LOW_25G_AUI_AOC_ACC BIT_ULL(28)
#define ICE_PHY_TYPE_LOW_25G_AUI_C2C BIT_ULL(29)
#define ICE_PHY_TYPE_LOW_40GBASE_CR4 BIT_ULL(30)
#define ICE_PHY_TYPE_LOW_40GBASE_SR4 BIT_ULL(31)
#define ICE_PHY_TYPE_LOW_40GBASE_LR4 BIT_ULL(32)
#define ICE_PHY_TYPE_LOW_40GBASE_KR4 BIT_ULL(33)
#define ICE_PHY_TYPE_LOW_40G_XLAUI_AOC_ACC BIT_ULL(34)
#define ICE_PHY_TYPE_LOW_40G_XLAUI BIT_ULL(35)
#define ICE_PHY_TYPE_LOW_50GBASE_CR2 BIT_ULL(36)
#define ICE_PHY_TYPE_LOW_50GBASE_SR2 BIT_ULL(37)
#define ICE_PHY_TYPE_LOW_50GBASE_LR2 BIT_ULL(38)
#define ICE_PHY_TYPE_LOW_50GBASE_KR2 BIT_ULL(39)
#define ICE_PHY_TYPE_LOW_50G_LAUI2_AOC_ACC BIT_ULL(40)
#define ICE_PHY_TYPE_LOW_50G_LAUI2 BIT_ULL(41)
#define ICE_PHY_TYPE_LOW_50G_AUI2_AOC_ACC BIT_ULL(42)
#define ICE_PHY_TYPE_LOW_50G_AUI2 BIT_ULL(43)
#define ICE_PHY_TYPE_LOW_50GBASE_CP BIT_ULL(44)
#define ICE_PHY_TYPE_LOW_50GBASE_SR BIT_ULL(45)
#define ICE_PHY_TYPE_LOW_50GBASE_FR BIT_ULL(46)
#define ICE_PHY_TYPE_LOW_50GBASE_LR BIT_ULL(47)
#define ICE_PHY_TYPE_LOW_50GBASE_KR_PAM4 BIT_ULL(48)
#define ICE_PHY_TYPE_LOW_50G_AUI1_AOC_ACC BIT_ULL(49)
#define ICE_PHY_TYPE_LOW_50G_AUI1 BIT_ULL(50)
#define ICE_PHY_TYPE_LOW_100GBASE_CR4 BIT_ULL(51)
#define ICE_PHY_TYPE_LOW_100GBASE_SR4 BIT_ULL(52)
#define ICE_PHY_TYPE_LOW_100GBASE_LR4 BIT_ULL(53)
#define ICE_PHY_TYPE_LOW_100GBASE_KR4 BIT_ULL(54)
#define ICE_PHY_TYPE_LOW_100G_CAUI4_AOC_ACC BIT_ULL(55)
#define ICE_PHY_TYPE_LOW_100G_CAUI4 BIT_ULL(56)
#define ICE_PHY_TYPE_LOW_100G_AUI4_AOC_ACC BIT_ULL(57)
#define ICE_PHY_TYPE_LOW_100G_AUI4 BIT_ULL(58)
#define ICE_PHY_TYPE_LOW_100GBASE_CR_PAM4 BIT_ULL(59)
#define ICE_PHY_TYPE_LOW_100GBASE_KR_PAM4 BIT_ULL(60)
#define ICE_PHY_TYPE_LOW_100GBASE_CP2 BIT_ULL(61)
#define ICE_PHY_TYPE_LOW_100GBASE_SR2 BIT_ULL(62)
#define ICE_PHY_TYPE_LOW_100GBASE_DR BIT_ULL(63)
#define ICE_PHY_TYPE_HIGH_100GBASE_KR2_PAM4 BIT_ULL(0)
#define ICE_PHY_TYPE_HIGH_100G_CAUI2_AOC_ACC BIT_ULL(1)
#define ICE_PHY_TYPE_HIGH_100G_CAUI2 BIT_ULL(2)
#define ICE_PHY_TYPE_HIGH_100G_AUI2_AOC_ACC BIT_ULL(3)
#define ICE_PHY_TYPE_HIGH_100G_AUI2 BIT_ULL(4)
#define ICE_PHY_TYPE_HIGH_200G_CR4_PAM4 BIT_ULL(5)
#define ICE_PHY_TYPE_HIGH_200G_SR4 BIT_ULL(6)
#define ICE_PHY_TYPE_HIGH_200G_FR4 BIT_ULL(7)
#define ICE_PHY_TYPE_HIGH_200G_LR4 BIT_ULL(8)
#define ICE_PHY_TYPE_HIGH_200G_DR4 BIT_ULL(9)
#define ICE_PHY_TYPE_HIGH_200G_KR4_PAM4 BIT_ULL(10)
#define ICE_PHY_TYPE_HIGH_200G_AUI4_AOC_ACC BIT_ULL(11)
#define ICE_PHY_TYPE_HIGH_200G_AUI4 BIT_ULL(12)
#define ICE_PHY_TYPE_HIGH_200G_AUI8_AOC_ACC BIT_ULL(13)
#define ICE_PHY_TYPE_HIGH_200G_AUI8 BIT_ULL(14)
#define ICE_PHY_TYPE_HIGH_400GBASE_FR8 BIT_ULL(15)
if (low & BIT_ULL(i))
if (high & BIT_ULL(i))
pt_low = BIT_ULL(index);
*phy_type_low |= BIT_ULL(index);
pt_high = BIT_ULL(index);
*phy_type_high |= BIT_ULL(index);
mask = BIT_ULL(ce_info->width) - 1;
mask = BIT_ULL(ce_info->width) - 1;
u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1);
*cur_stat += (new_data + BIT_ULL(40)) - *prev_stat;
*cur_stat += (new_data + BIT_ULL(32)) - *prev_stat;
#ifndef BIT_ULL
(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4))
(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP))
(BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP))
ICE_FLOW_AVF_RSS_IPV4_MASKS | BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP))
(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6))
(BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP))
(BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP))
ICE_FLOW_AVF_RSS_IPV6_MASKS | BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP))
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP)) {
~BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP);
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP)) {
~BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP);
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_SCTP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_OTHER) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV4) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_SCTP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_OTHER) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_FRAG_IPV6) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV4_TCP_SYN_NO_ACK) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV4_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV4_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_IPV6_TCP_SYN_NO_ACK) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_UNICAST_IPV6_UDP) | \
BIT_ULL(ICE_AVF_FLOW_FIELD_MULTICAST_IPV6_UDP))
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_SA) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV4_DA))
(BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_SA) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_IPV6_DA))
(BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_SRC_PORT) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_TCP_DST_PORT))
(BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_SRC_PORT) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_UDP_DST_PORT))
(BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_SRC_PORT) | \
BIT_ULL(ICE_FLOW_FIELD_IDX_SCTP_DST_PORT))
#define ICE_TXD_CTX_UDP_TUNNELING BIT_ULL(ICE_TXD_CTX_QW0_L4TUNT_S)
#define ICE_TXD_CTX_QW0_EIP_NOINC_M BIT_ULL(ICE_TXD_CTX_QW0_EIP_NOINC_S)
#define ICE_TXD_CTX_QW0_L4T_CS_M BIT_ULL(ICE_TXD_CTX_QW0_L4T_CS_S)
#define ICE_FXD_FLTR_QW0_COMP_Q_M BIT_ULL(ICE_FXD_FLTR_QW0_COMP_Q_S)
#define ICE_FXD_FLTR_QW0_EVICT_ENA_M BIT_ULL(ICE_FXD_FLTR_QW0_EVICT_ENA_S)
#define ICE_FXD_FLTR_QW0_DROP_M BIT_ULL(ICE_FXD_FLTR_QW0_DROP_S)
#define ICE_FXD_FLTR_QW1_PCMD_M BIT_ULL(ICE_FXD_FLTR_QW1_PCMD_S)
#define ICE_FXD_FLTR_QW1_SWAP_M BIT_ULL(ICE_FXD_FLTR_QW1_SWAP_S)
#define ICE_RXD_QW1_STATUS_TSYNVALID_M BIT_ULL(ICE_RXD_QW1_STATUS_TSYNVALID_S)
#define ICE_RXD_QW1_LEN_SPH_M BIT_ULL(ICE_RXD_QW1_LEN_SPH_S)
uint64_t type = BIT_ULL(bit);
uint64_t type = BIT_ULL(bit);
u64 pow_result = BIT_ULL(i);
#define ICE_DBG_TRACE BIT_ULL(0) /* for function-trace only */
#define ICE_DBG_INIT BIT_ULL(1)
#define ICE_DBG_RELEASE BIT_ULL(2)
#define ICE_DBG_FW_LOG BIT_ULL(3)
#define ICE_DBG_LINK BIT_ULL(4)
#define ICE_DBG_PHY BIT_ULL(5)
#define ICE_DBG_QCTX BIT_ULL(6)
#define ICE_DBG_NVM BIT_ULL(7)
#define ICE_DBG_LAN BIT_ULL(8)
#define ICE_DBG_FLOW BIT_ULL(9)
#define ICE_DBG_DCB BIT_ULL(10)
#define ICE_DBG_DIAG BIT_ULL(11)
#define ICE_DBG_FD BIT_ULL(12)
#define ICE_DBG_SW BIT_ULL(13)
#define ICE_DBG_SCHED BIT_ULL(14)
#define ICE_DBG_RDMA BIT_ULL(15)
#define ICE_DBG_PKG BIT_ULL(16)
#define ICE_DBG_RES BIT_ULL(17)
#define ICE_DBG_AQ_MSG BIT_ULL(24)
#define ICE_DBG_AQ_DESC BIT_ULL(25)
#define ICE_DBG_AQ_DESC_BUF BIT_ULL(26)
#define ICE_DBG_AQ_CMD BIT_ULL(27)
#define ICE_DBG_PARSER BIT_ULL(28)
#define ICE_DBG_USER BIT_ULL(31)
#define LFC_ENABLE BIT_ULL(8)
#define ICRDMA_CCQPSTATUS_CCQP_DONE BIT_ULL(0)
#define ICRDMA_CCQPSTATUS_CCQP_ERR BIT_ULL(31)
#define IRDMAQPC_INSERTL2TAG2 BIT_ULL(11)
#define IRDMAQPC_ECN_EN BIT_ULL(14)
#define IRDMAQPC_DROPOOOSEG BIT_ULL(15)
#define IRDMAQPC_ERR_RQ_IDX_VALID BIT_ULL(19)
#define IRDMAQPC_DC_TCP_EN BIT_ULL(25)
#define IRDMAQPC_RCVTPHEN BIT_ULL(28)
#define IRDMAQPC_XMITTPHEN BIT_ULL(29)
#define IRDMAQPC_RQTPHEN BIT_ULL(30)
#define IRDMAQPC_SQTPHEN BIT_ULL(31)
#define IRDMAQPC_PMENA BIT_ULL(47)
#define IRDMAQPC_AVOIDSTRETCHACK BIT_ULL(23)
#define IRDMAQPC_WSCALE BIT_ULL(20)
#define IRDMAQPC_KEEPALIVE BIT_ULL(21)
#define IRDMAQPC_IGNORE_TCP_OPT BIT_ULL(22)
#define IRDMAQPC_IGNORE_TCP_UNS_OPT BIT_ULL(23)
#define IRDMAQPC_UDPRIVCQENABLE BIT_ULL(19)
#define IRDMAQPC_WRRDRSPOK BIT_ULL(20)
#define IRDMAQPC_RDOK BIT_ULL(21)
#define IRDMAQPC_SNDMARKERS BIT_ULL(22)
#define IRDMAQPC_DCQCNENABLE BIT_ULL(22)
#define IRDMAQPC_FW_CC_ENABLE BIT_ULL(28)
#define IRDMAQPC_RCVNOICRC BIT_ULL(31)
#define IRDMAQPC_BINDEN BIT_ULL(23)
#define IRDMAQPC_FASTREGEN BIT_ULL(24)
#define IRDMAQPC_PRIVEN BIT_ULL(25)
#define IRDMAQPC_TIMELYENABLE BIT_ULL(27)
#define IRDMAQPC_USESTATSINSTANCE BIT_ULL(26)
#define IRDMAQPC_IWARPMODE BIT_ULL(28)
#define IRDMAQPC_RCVMARKERS BIT_ULL(29)
#define IRDMAQPC_ALIGNHDRS BIT_ULL(30)
#define IRDMAQPC_RCVNOMPACRC BIT_ULL(31)
#define IRDMAQPSQ_COPY_HOST_PBL BIT_ULL(43)
#define IRDMAQPSQ_PUSHWQE BIT_ULL(56)
#define IRDMAQPSQ_STREAMMODE BIT_ULL(58)
#define IRDMAQPSQ_WAITFORRCVPDU BIT_ULL(59)
#define IRDMAQPSQ_READFENCE BIT_ULL(60)
#define IRDMAQPSQ_LOCALFENCE BIT_ULL(61)
#define IRDMAQPSQ_UDPHEADER BIT_ULL(61)
#define IRDMAQPSQ_SIGCOMPL BIT_ULL(62)
#define IRDMAQPSQ_VALID BIT_ULL(63)
#define IRDMAQPSQ_FRAG_VALID BIT_ULL(63)
#define IRDMAQPSQ_INLINEDATAFLAG BIT_ULL(57)
#define IRDMAQPSQ_IMMDATAFLAG BIT_ULL(47)
#define IRDMAQPSQ_REPORTRTT BIT_ULL(46)
#define IRDMAQPSQ_VABASEDTO BIT_ULL(53)
#define IRDMAQPSQ_MEMWINDOWTYPE BIT_ULL(54)
#define IRDMAQPSQ_COPYHOSTPBLS BIT_ULL(43)
#define IRDMA_FEATURE_RTS_AE BIT_ULL(0)
#define IRDMA_FEATURE_CQ_RESIZE BIT_ULL(1)
#define IRDMA_FEATURE_RELAX_RQ_ORDER BIT_ULL(2)
#define IRDMA_FEATURE_64_BYTE_CQE BIT_ULL(5)
#define IRDMA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
#define IRDMA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
#define IRDMA_CQPSQ_QHASH_VLANVALID BIT_ULL(59)
#define IRDMA_CQPSQ_STATS_WQEVALID BIT_ULL(63)
#define IRDMA_CQPSQ_STATS_ALLOC_INST BIT_ULL(62)
#define IRDMA_CQPSQ_STATS_USE_HMC_FCN_INDEX BIT_ULL(60)
#define IRDMA_CQPSQ_STATS_USE_INST BIT_ULL(61)
#define IRDMA_CQPSQ_WS_WQEVALID BIT_ULL(63)
#define IRDMA_CQPSQ_WS_ENABLENODE BIT_ULL(62)
#define IRDMA_CQPSQ_WS_NODETYPE BIT_ULL(61)
#define IRDMA_CQPSQ_UP_WQEVALID BIT_ULL(63)
#define IRDMA_CQPSQ_UP_USEVLAN BIT_ULL(62)
#define IRDMA_CQPSQ_UP_USEOVERRIDE BIT_ULL(61)
#define IRDMA_CQPSQ_QUERY_RDMA_FEATURES_WQEVALID BIT_ULL(63)
#define IRDMA_CQPHC_DISABLE_PFPDUS BIT_ULL(1)
#define IRDMA_CQPHC_ROCEV2_RTO_POLICY BIT_ULL(2)
#define IRDMA_CQPHC_CC_CFG_VALID BIT_ULL(31)
#define IRDMA_CQPHC_EN_REM_ENDPOINT_TRK BIT_ULL(3)
#define IRDMA_CQ_DBSA_ARM_NEXT BIT_ULL(14)
#define IRDMA_CQ_DBSA_ARM_NEXT_SE BIT_ULL(15)
#define IRDMA_CQ_EXTCQE BIT_ULL(50)
#define IRDMA_OOO_CMPL BIT_ULL(54)
#define IRDMA_CQ_ERROR BIT_ULL(55)
#define IRDMA_CQ_SQ BIT_ULL(62)
#define IRDMA_CQ_VALID BIT_ULL(63)
#define IRDMA_CQ_IMMVALID BIT_ULL(62)
#define IRDMA_CQ_UDSMACVALID BIT_ULL(61)
#define IRDMA_CQ_UDVLANVALID BIT_ULL(60)
#define IRDMACQ_PSHDROP BIT_ULL(51)
#define IRDMACQ_STAG BIT_ULL(53)
#define IRDMACQ_IPV4 BIT_ULL(53)
#define IRDMACQ_SOEVENT BIT_ULL(54)
#define IRDMA_CEQE_VALID BIT_ULL(63)
#define IRDMA_AEQE_QPCQID_HI BIT_ULL(46)
#define IRDMA_AEQE_OVERFLOW BIT_ULL(33)
#define IRDMA_AEQE_VALID BIT_ULL(63)
#define IRDMA_UDA_QPSQ_VALID BIT_ULL(63)
#define IRDMA_UDA_QPSQ_SIGCOMPL BIT_ULL(62)
#define IRDMA_VLAN_TAG_VALID BIT_ULL(50)
#define IRDMA_UDA_QPSQ_DOLOOPBACK BIT_ULL(44)
#define IRDMA_CQPSQ_WQEVALID BIT_ULL(63)
#define IRDMA_CQPSQ_TPHEN BIT_ULL(60)
#define IRDMA_CQPSQ_QP_ORDVALID BIT_ULL(42)
#define IRDMA_CQPSQ_QP_TOECTXVALID BIT_ULL(43)
#define IRDMA_CQPSQ_QP_CACHEDVARVALID BIT_ULL(44)
#define IRDMA_CQPSQ_QP_VQ BIT_ULL(45)
#define IRDMA_CQPSQ_QP_FORCELOOPBACK BIT_ULL(46)
#define IRDMA_CQPSQ_QP_CQNUMVALID BIT_ULL(47)
#define IRDMA_CQPSQ_QP_MACVALID BIT_ULL(51)
#define IRDMA_CQPSQ_QP_MSSCHANGE BIT_ULL(52)
#define IRDMA_CQPSQ_QP_IGNOREMWBOUND BIT_ULL(54)
#define IRDMA_CQPSQ_QP_REMOVEHASHENTRY BIT_ULL(55)
#define IRDMA_CQPSQ_QP_RESETCON BIT_ULL(58)
#define IRDMA_CQPSQ_QP_ARPTABIDXVALID BIT_ULL(59)
#define IRDMA_CQPSQ_CQ_CQRESIZE BIT_ULL(43)
#define IRDMA_CQPSQ_CQ_CHKOVERFLOW BIT_ULL(46)
#define IRDMA_CQPSQ_CQ_VIRTMAP BIT_ULL(47)
#define IRDMA_CQPSQ_CQ_ENCEQEMASK BIT_ULL(48)
#define IRDMA_CQPSQ_CQ_CEQIDVALID BIT_ULL(49)
#define IRDMA_CQPSQ_CQ_AVOIDMEMCNFLCT BIT_ULL(61)
#define IRDMA_CQPSQ_STAG_MR BIT_ULL(43)
#define IRDMA_CQPSQ_STAG_MWTYPE BIT_ULL(42)
#define IRDMA_CQPSQ_STAG_SKIPFLUSH BIT_ULL(40)
#define IRDMA_CQPSQ_STAG_MW1_BIND_DONT_VLDT_KEY BIT_ULL(58)
#define IRDMA_CQPSQ_STAG_REMACCENABLED BIT_ULL(53)
#define IRDMA_CQPSQ_STAG_VABASEDTO BIT_ULL(59)
#define IRDMA_CQPSQ_STAG_USEHMCFNIDX BIT_ULL(60)
#define IRDMA_CQPSQ_MLM_FREEENTRY BIT_ULL(62)
#define IRDMA_CQPSQ_MLM_IGNORE_REF_CNT BIT_ULL(61)
#define IRDMA_CQPSQ_MAT_ENTRYVALID BIT_ULL(42)
#define IRDMA_CQPSQ_MAT_PERMANENT BIT_ULL(43)
#define IRDMA_CQPSQ_MAT_QUERY BIT_ULL(44)
#define IRDMA_CQPSQ_MVPBP_INV_PD_ENT BIT_ULL(62)
#define IRDMA_CQPSQ_MPP_FREE_PAGE BIT_ULL(62)
#define IRDMA_CQPSQ_UCTX_RAWFORMAT BIT_ULL(61)
#define IRDMA_CQPSQ_UCTX_FREEZEQP BIT_ULL(62)
#define IRDMA_CQPSQ_MHMC_FREEPMFN BIT_ULL(62)
#define IRDMA_CQPSQ_CEQ_VMAP BIT_ULL(47)
#define IRDMA_CQPSQ_CEQ_ITRNOEXPIRE BIT_ULL(46)
#define IRDMA_CQPSQ_AEQ_VMAP BIT_ULL(47)
#define IRDMA_CQPSQ_CFPM_HW_FLUSH_TIMER_DISABLE BIT_ULL(43)
#define IRDMA_CQPSQ_FWQE_GENERATE_AE BIT_ULL(59)
#define IRDMA_CQPSQ_FWQE_USERFLCODE BIT_ULL(60)
#define IRDMA_CQPSQ_FWQE_FLUSHSQ BIT_ULL(61)
#define IRDMA_CQPSQ_FWQE_FLUSHRQ BIT_ULL(62)
#define IRDMA_CQPSQ_MAPT_ADDPORT BIT_ULL(62)
#define IRDMA_CQPSQ_UPESD_ENTRY_VALID BIT_ULL(63)
#define IRDMA_CQPSQ_UPESD_SKIP_ENTRY BIT_ULL(7)
#define IRDMAQPC_IBRDENABLE BIT_ULL(2)
#define IRDMAQPC_IPV4 BIT_ULL(3)
#define IRDMAQPC_NONAGLE BIT_ULL(4)
#define IRDMAQPC_INSERTVLANTAG BIT_ULL(5)
#define IRDMAQPC_ISQP1 BIT_ULL(6)
#define IRDMAQPC_TIMESTAMP BIT_ULL(7)
BIT_ULL(IB_USER_VERBS_CMD_ATTACH_MCAST) |
BIT_ULL(IB_USER_VERBS_CMD_CREATE_AH) |
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_AH) |
BIT_ULL(IB_USER_VERBS_CMD_DETACH_MCAST);
BIT_ULL(IB_USER_VERBS_CMD_GET_CONTEXT) |
BIT_ULL(IB_USER_VERBS_CMD_QUERY_DEVICE) |
BIT_ULL(IB_USER_VERBS_CMD_QUERY_PORT) |
BIT_ULL(IB_USER_VERBS_CMD_ALLOC_PD) |
BIT_ULL(IB_USER_VERBS_CMD_DEALLOC_PD) |
BIT_ULL(IB_USER_VERBS_CMD_REG_MR) |
BIT_ULL(IB_USER_VERBS_CMD_REREG_MR) |
BIT_ULL(IB_USER_VERBS_CMD_DEREG_MR) |
BIT_ULL(IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
BIT_ULL(IB_USER_VERBS_CMD_CREATE_CQ) |
BIT_ULL(IB_USER_VERBS_CMD_RESIZE_CQ) |
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_CQ) |
BIT_ULL(IB_USER_VERBS_CMD_REQ_NOTIFY_CQ) |
BIT_ULL(IB_USER_VERBS_CMD_CREATE_QP) |
BIT_ULL(IB_USER_VERBS_CMD_MODIFY_QP) |
BIT_ULL(IB_USER_VERBS_CMD_QUERY_QP) |
BIT_ULL(IB_USER_VERBS_CMD_POLL_CQ) |
BIT_ULL(IB_USER_VERBS_CMD_DESTROY_QP) |
BIT_ULL(IB_USER_VERBS_CMD_POST_RECV) |
BIT_ULL(IB_USER_VERBS_CMD_POST_SEND);
BIT_ULL(IB_USER_VERBS_EX_CMD_MODIFY_QP) |
BIT_ULL(IB_USER_VERBS_EX_CMD_QUERY_DEVICE);
iwdev->ibdev.uverbs_ex_cmd_mask |= BIT_ULL(IB_USER_VERBS_EX_CMD_CREATE_CQ);
#define IRDMA_UDAQPC_DCTCPENABLE BIT_ULL(25)
#define IRDMA_UDAQPC_INSERTTAG2 BIT_ULL(11)
#define IRDMA_UDAQPC_INSERTTAG3 BIT_ULL(14)
#define IRDMA_UDAQPC_PRIVILEGEENABLE BIT_ULL(25)
#define IRDMA_UDAQPC_USE_STATISTICS_INSTANCE BIT_ULL(26)
#define IRDMA_UDAQPC_PRIVHDRGENENABLE BIT_ULL(0)
#define IRDMA_UDAQPC_RQHDRSPLITENABLE BIT_ULL(3)
#define IRDMA_UDAQPC_RQHDRRINGBUFENABLE BIT_ULL(2)
#define IRDMA_UDAQPC_SQHDRRINGBUFENABLE BIT_ULL(1)
#define IRDMA_UDA_CQPSQ_MAV_WQEVALID BIT_ULL(63)
#define IRDMA_UDA_CQPSQ_MAV_DOLOOPBACKK BIT_ULL(62)
#define IRDMA_UDA_CQPSQ_MAV_IPV4VALID BIT_ULL(59)
#define IRDMA_UDA_CQPSQ_MAV_INSERTVLANTAG BIT_ULL(60)
#define IRDMA_UDA_MGCTX_VFFLAG BIT_ULL(29)
#define IRDMA_UDA_MGCTX_VALIDENT BIT_ULL(31)
#define IRDMA_UDA_MGCTX_FLAGIGNOREDPORT BIT_ULL(30)
#define IRDMA_UDA_CQPSQ_MG_WQEVALID BIT_ULL(63)
#define IRDMA_UDA_CQPSQ_MG_IPV4VALID BIT_ULL(60)
#define IRDMA_UDA_CQPSQ_MG_VLANVALID BIT_ULL(59)
#define IRDMA_UDA_CQPSQ_QHASH_ BIT_ULL(0)
#define IRDMA_UDA_CQPSQ_QHASH_WQEVALID BIT_ULL(63)
#define IRDMA_UDA_CQPSQ_QHASH_IPV4VALID BIT_ULL(60)
#define IRDMA_UDA_CQPSQ_QHASH_LANFWD BIT_ULL(59)
#define IRDMA_UDA_QPSQ_PUSHWQE BIT_ULL(56)
#define IRDMA_UDA_QPSQ_INLINEDATAFLAG BIT_ULL(57)
#define IRDMA_UDA_QPSQ_NOCHECKSUM BIT_ULL(45)
#define IRDMA_UDA_QPSQ_AHIDXVALID BIT_ULL(46)
#define IRDMA_UDA_QPSQ_LOCAL_FENCE BIT_ULL(61)
#define IRDMA_UDA_QPSQ_MULTICAST BIT_ULL(63)
#define IRDMA_UDA_QPSQ_FWD_PROG_CONFIRM BIT_ULL(45)
#define IRDMA_UDAQPC_IPV4 BIT_ULL(3)
#define IRDMA_UDAQPC_INSERTVLANTAG BIT_ULL(5)
#define IRDMA_UDAQPC_ISQP1 BIT_ULL(6)
#define IRDMA_UDAQPC_ECNENABLE BIT_ULL(14)
bits_needed = DIV_ROUND_UP_ULL(mem_size, BIT_ULL(pprm->pble_shift));
#ifndef BIT_ULL
#define IXGBE_PHY_TYPE_LOW_100BASE_TX BIT_ULL(0)
#define IXGBE_PHY_TYPE_LOW_100M_SGMII BIT_ULL(1)
#define IXGBE_PHY_TYPE_LOW_1000BASE_T BIT_ULL(2)
#define IXGBE_PHY_TYPE_LOW_1000BASE_SX BIT_ULL(3)
#define IXGBE_PHY_TYPE_LOW_1000BASE_LX BIT_ULL(4)
#define IXGBE_PHY_TYPE_LOW_1000BASE_KX BIT_ULL(5)
#define IXGBE_PHY_TYPE_LOW_1G_SGMII BIT_ULL(6)
#define IXGBE_PHY_TYPE_LOW_2500BASE_T BIT_ULL(7)
#define IXGBE_PHY_TYPE_LOW_2500BASE_X BIT_ULL(8)
#define IXGBE_PHY_TYPE_LOW_2500BASE_KX BIT_ULL(9)
#define IXGBE_PHY_TYPE_LOW_5GBASE_T BIT_ULL(10)
#define IXGBE_PHY_TYPE_LOW_5GBASE_KR BIT_ULL(11)
#define IXGBE_PHY_TYPE_LOW_10GBASE_T BIT_ULL(12)
#define IXGBE_PHY_TYPE_LOW_10G_SFI_DA BIT_ULL(13)
#define IXGBE_PHY_TYPE_LOW_10GBASE_SR BIT_ULL(14)
#define IXGBE_PHY_TYPE_LOW_10GBASE_LR BIT_ULL(15)
#define IXGBE_PHY_TYPE_LOW_10GBASE_KR_CR1 BIT_ULL(16)
#define IXGBE_PHY_TYPE_LOW_10G_SFI_AOC_ACC BIT_ULL(17)
#define IXGBE_PHY_TYPE_LOW_10G_SFI_C2C BIT_ULL(18)
#define IXGBE_PHY_TYPE_HIGH_10BASE_T BIT_ULL(1)
#define IXGBE_PHY_TYPE_HIGH_10M_SGMII BIT_ULL(2)
#define IXGBE_PHY_TYPE_HIGH_2500M_SGMII BIT_ULL(56)
#define IXGBE_PHY_TYPE_HIGH_100M_USXGMII BIT_ULL(57)
#define IXGBE_PHY_TYPE_HIGH_1G_USXGMII BIT_ULL(58)
#define IXGBE_PHY_TYPE_HIGH_2500M_USXGMII BIT_ULL(59)
#define IXGBE_PHY_TYPE_HIGH_5G_USXGMII BIT_ULL(60)
#define IXGBE_PHY_TYPE_HIGH_10G_USXGMII BIT_ULL(61)
#define I40E_PHY_TYPES_BITMASK (BIT_ULL(I40E_PHY_TYPE_SGMII) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_KX) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_KR) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4) | \
BIT_ULL(I40E_PHY_TYPE_XAUI) | \
BIT_ULL(I40E_PHY_TYPE_XFI) | \
BIT_ULL(I40E_PHY_TYPE_SFI) | \
BIT_ULL(I40E_PHY_TYPE_XLAUI) | \
BIT_ULL(I40E_PHY_TYPE_XLPPI) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_UNRECOGNIZED) | \
BIT_ULL(I40E_PHY_TYPE_UNSUPPORTED) | \
BIT_ULL(I40E_PHY_TYPE_100BASE_TX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_T) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_T) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_SR) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_LR) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU) | \
BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4) | \
BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_SX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_LX) | \
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL) | \
BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_KR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_CR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_SR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_LR) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC) | \
BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC) | \
BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T) | \
BIT_ULL(I40E_PHY_TYPE_5GBASE_T))
(u32)((tx_counter + BIT_ULL(32)) - *tx_offset);
(u32)((rx_counter + BIT_ULL(32)) - *rx_offset);
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
val3 = (sd_index) | BIT_ULL(I40E_PFHMC_SDCMD_PMSDWR_SHIFT); \
mask = BIT_ULL(ce_info->width) - 1;
obj->size = BIT_ULL(size_exp);
obj->size = BIT_ULL(size_exp);
obj->size = BIT_ULL(size_exp);
obj->size = BIT_ULL(size_exp);
mask = BIT_ULL(ce_info->width) - 1;
#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
#define I40E_TXD_FLTR_QW1_ATR_MASK BIT_ULL(I40E_TXD_FLTR_QW1_ATR_SHIFT)
#define I40E_CAP_PHY_TYPE_SGMII BIT_ULL(I40E_PHY_TYPE_SGMII)
#define I40E_CAP_PHY_TYPE_1000BASE_KX BIT_ULL(I40E_PHY_TYPE_1000BASE_KX)
#define I40E_CAP_PHY_TYPE_10GBASE_KX4 BIT_ULL(I40E_PHY_TYPE_10GBASE_KX4)
#define I40E_CAP_PHY_TYPE_10GBASE_KR BIT_ULL(I40E_PHY_TYPE_10GBASE_KR)
#define I40E_CAP_PHY_TYPE_40GBASE_KR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_KR4)
#define I40E_CAP_PHY_TYPE_XAUI BIT_ULL(I40E_PHY_TYPE_XAUI)
#define I40E_CAP_PHY_TYPE_XFI BIT_ULL(I40E_PHY_TYPE_XFI)
#define I40E_CAP_PHY_TYPE_SFI BIT_ULL(I40E_PHY_TYPE_SFI)
#define I40E_CAP_PHY_TYPE_XLAUI BIT_ULL(I40E_PHY_TYPE_XLAUI)
#define I40E_CAP_PHY_TYPE_XLPPI BIT_ULL(I40E_PHY_TYPE_XLPPI)
#define I40E_CAP_PHY_TYPE_40GBASE_CR4_CU BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_CR1_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_AOC BIT_ULL(I40E_PHY_TYPE_10GBASE_AOC)
#define I40E_CAP_PHY_TYPE_40GBASE_AOC BIT_ULL(I40E_PHY_TYPE_40GBASE_AOC)
#define I40E_CAP_PHY_TYPE_100BASE_TX BIT_ULL(I40E_PHY_TYPE_100BASE_TX)
#define I40E_CAP_PHY_TYPE_1000BASE_T BIT_ULL(I40E_PHY_TYPE_1000BASE_T)
#define I40E_CAP_PHY_TYPE_10GBASE_T BIT_ULL(I40E_PHY_TYPE_10GBASE_T)
#define I40E_CAP_PHY_TYPE_10GBASE_SR BIT_ULL(I40E_PHY_TYPE_10GBASE_SR)
#define I40E_CAP_PHY_TYPE_10GBASE_LR BIT_ULL(I40E_PHY_TYPE_10GBASE_LR)
#define I40E_CAP_PHY_TYPE_10GBASE_SFPP_CU BIT_ULL(I40E_PHY_TYPE_10GBASE_SFPP_CU)
#define I40E_CAP_PHY_TYPE_10GBASE_CR1 BIT_ULL(I40E_PHY_TYPE_10GBASE_CR1)
#define I40E_CAP_PHY_TYPE_40GBASE_CR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_CR4)
#define I40E_CAP_PHY_TYPE_40GBASE_SR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_SR4)
#define I40E_CAP_PHY_TYPE_40GBASE_LR4 BIT_ULL(I40E_PHY_TYPE_40GBASE_LR4)
#define I40E_CAP_PHY_TYPE_1000BASE_SX BIT_ULL(I40E_PHY_TYPE_1000BASE_SX)
#define I40E_CAP_PHY_TYPE_1000BASE_LX BIT_ULL(I40E_PHY_TYPE_1000BASE_LX)
BIT_ULL(I40E_PHY_TYPE_1000BASE_T_OPTICAL)
#define I40E_CAP_PHY_TYPE_20GBASE_KR2 BIT_ULL(I40E_PHY_TYPE_20GBASE_KR2)
#define I40E_CAP_PHY_TYPE_25GBASE_KR BIT_ULL(I40E_PHY_TYPE_25GBASE_KR + \
#define I40E_CAP_PHY_TYPE_25GBASE_CR BIT_ULL(I40E_PHY_TYPE_25GBASE_CR + \
#define I40E_CAP_PHY_TYPE_25GBASE_SR BIT_ULL(I40E_PHY_TYPE_25GBASE_SR + \
#define I40E_CAP_PHY_TYPE_25GBASE_LR BIT_ULL(I40E_PHY_TYPE_25GBASE_LR + \
#define I40E_CAP_PHY_TYPE_25GBASE_AOC BIT_ULL(I40E_PHY_TYPE_25GBASE_AOC + \
#define I40E_CAP_PHY_TYPE_25GBASE_ACC BIT_ULL(I40E_PHY_TYPE_25GBASE_ACC + \
#define I40E_CAP_PHY_TYPE_2_5GBASE_T BIT_ULL(I40E_PHY_TYPE_2_5GBASE_T)
#define I40E_CAP_PHY_TYPE_5GBASE_T BIT_ULL(I40E_PHY_TYPE_5GBASE_T)
#define I40E_HW_FLAG_AQ_SRCTL_ACCESS_ENABLE BIT_ULL(0)
#define I40E_HW_FLAG_802_1AD_CAPABLE BIT_ULL(1)
#define I40E_HW_FLAG_AQ_PHY_ACCESS_CAPABLE BIT_ULL(2)
#define I40E_HW_FLAG_NVM_READ_REQUIRES_LOCK BIT_ULL(3)
#define I40E_HW_FLAG_FW_LLDP_STOPPABLE BIT_ULL(4)
#define I40E_HW_FLAG_FW_LLDP_PERSISTENT BIT_ULL(5)
#define I40E_HW_FLAG_AQ_PHY_ACCESS_EXTENDED BIT_ULL(6)
#define I40E_HW_FLAG_DROP_MODE BIT_ULL(7)
#define I40E_HW_FLAG_X722_FEC_REQUEST_CAPABLE BIT_ULL(8)
#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_UDP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_SCTP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_OTHER) | \
BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV4) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_UDP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_SCTP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_OTHER) | \
BIT_ULL(I40E_FILTER_PCTYPE_FRAG_IPV6) | \
BIT_ULL(I40E_FILTER_PCTYPE_L2_PAYLOAD))
BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK) | \
BIT_ULL(I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK))
if (oct->io_qmask.iq64B & BIT_ULL(q_no - srn)) {
if (oct->io_qmask.iq & BIT_ULL(q_no - srn)) {
if (oct->io_qmask.oq & BIT_ULL(q_no - srn)) {
while (!(d64 & BIT_ULL(q_no)) && loop--) {
while (!(d64 & BIT_ULL(q_no)) && loop--) {
#define LIO_CN23XX_PKT_MAC_CTL_RINFO_TRS BIT_ULL(16)
#define LIO_CN23XX_PKT_INPUT_CTL_VF_NUM BIT_ULL(32)
#define LIO_CN23XX_INTR_PO_INT BIT_ULL(63)
#define LIO_CN23XX_INTR_PI_INT BIT_ULL(62)
#define LIO_CN23XX_INTR_RESEND BIT_ULL(60)
#define LIO_CN23XX_INTR_CINT_ENB BIT_ULL(48)
#define LIO_CN23XX_INTR_DMA0_FORCE BIT_ULL(32)
#define LIO_CN23XX_INTR_DMA1_FORCE BIT_ULL(33)
#define LIO_CN23XX_INTR_DMA0_TIME BIT_ULL(36)
#define LIO_CN23XX_INTR_DMA1_TIME BIT_ULL(37)
#define LIO_CN23XX_INTR_DMAPF_ERR BIT_ULL(59)
#define LIO_CN23XX_INTR_PKTPF_ERR BIT_ULL(61)
#define LIO_CN23XX_INTR_PPPF_ERR BIT_ULL(63)
if ((oct->io_qmask.oq & BIT_ULL(i)) && (oct->droq[i]))
if ((oct->io_qmask.iq & BIT_ULL(i)) && (oct->instr_queue[i]))
(oct->io_qmask.iq & BIT_ULL(q_no)))
(oct->io_qmask.oq & BIT_ULL(q_no)))
oct->io_qmask.oq |= BIT_ULL(q_no);
oct->io_qmask.iq |= BIT_ULL(iq_no);
if (!(oct->io_qmask.iq & BIT_ULL(i)))
if (!(oct->io_qmask.oq & BIT_ULL(oq_no)))
if (!(oct->io_qmask.oq & BIT_ULL(i)))
if (!(oct->io_qmask.oq & BIT_ULL(i)))
if (!(oct->io_qmask.iq & BIT_ULL(i)))
if (!(oct->io_qmask.iq & BIT_ULL(i)))
if (!(oct->io_qmask.oq & BIT_ULL(i)))
if (!(oct->io_qmask.iq & BIT_ULL(i)))
if (!(oct_dev->io_qmask.iq & BIT_ULL(i)))
if (!(oct_dev->io_qmask.oq & BIT_ULL(i)))
data.bitwise_data = cpu_to_be64(BIT_ULL(54));
BIT_ULL(def->write.command_num));
BIT_ULL(def->write.command_num));
IB_SA_WELL_KNOWN_GUID = BIT_ULL(57) | 2,