BIT_9
#define GLB_GPIO_RAND_BIT_1 BIT_9 /* Random Bit 1 */
#define RI_CLR_RD_PERR BIT_9 /* Clear IRQ RAM Read Parity Err */
#define BMU_STOP BIT_9 /* Stop Rx/Tx Queue */
#define WOL_CTL_ENA_PME_ON_MAGIC_PKT BIT_9
#define PHY_M_AN_100_T4 BIT_9 /* Not cap. 100Base-T4 (always 0) */
#define PHY_M_1000C_AFD BIT_9 /* Advertise Full Duplex */
#define PHY_M_PC_DIS_SCRAMB BIT_9 /* Disable Scrambler */
#define PHY_M_IS_SYMB_ERROR BIT_9 /* Symbol Error */
#define PHY_M_DIS_AUT_MED BIT_9 /* Disable Aut. Medium Reg. Selection */
#define PHY_M_FIB_SIGD_POL BIT_9 /* SIGDET Polarity */
#define GM_GPSR_EXC_COL BIT_9 /* Excessive Collisions Occurred */
#define GM_GPCR_LOOP_ENA BIT_9 /* Enable MAC Loopback Mode */
#define GM_SMOD_VLAN_ENA BIT_9 /* Enable VLAN (Max. Frame Len) */
#define GMR_FS_BC BIT_9 /* Broadcast Packet */
#define GMF_RP_TST_OFF BIT_9 /* Read Pointer Test Off */
#define Y2_ASF_HCU_CCSR_AHB_RST BIT_9 /* Reset AHB bridge */
#define GMC_BYP_RETR_ON BIT_9 /* Bypass MAC retransmit FIFO On */
#define GPC_PHYADDR_1 BIT_9 /* Bit 1 of Phy Addr */
#define PCI_BURST_DIS BIT_9 /* Burst Disable */
#define PCI_PATCH_DIR_1 BIT_9
#define PCI_GAT_GPHY_N_REC_PACKET BIT_9 /* GPHY Not Received Packet */
#define PEX_DC_EN_PHANTOM BIT_9 /* Enable Phantom Functions */
#define Y2_LED_STAT_ON BIT_9 /* Status LED On (YUKON-2 only) */
#define Y2_IS_CHK_TXS2 BIT_9 /* Descriptor error TXS 2 */
#define Y2_IS_TCP_TXS2 BIT_9 /* TCP length mismatch sync Tx queue IRQ */
#define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9
#define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9
#define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9
#define Q81_CTL_HCS_HTR_INTR BIT_9
#define Q81_CTL_STATUS_F1E BIT_9
#define Q81_CTL_RD_CAM_BIT1 BIT_9
#define Q81_RSS_ICB_FLAGS_LI BIT_9