BIT_6
#define TXA_DIS_FSYNC BIT_6 /* Disable force of sync Tx queue */
#define BMU_FIFO_OP_OFF BIT_6 /* FIFO Operational Off */
#define RB_WP_T_ON BIT_6 /* Write Pointer Test On */
#define WOL_CTL_DIS_PME_ON_PATTERN BIT_6
#define PHY_M_AN_10_FD BIT_6 /* Advertise 10Base-TX Full Duplex */
#define PHY_M_AN_1000X_AHD BIT_6 /* Advertise 10000Base-X Half Duplex */
#define PHY_M_PC_SH_TP_SEL BIT_6 /* Shielded Twisted Pair Select */
#define PHY_M_PS_MDI_X_STAT BIT_6 /* MDI Crossover Stat (1=MDIX) */
#define PHY_M_IS_MDI_CHANGE BIT_6 /* MDI Crossover Changed */
#define PHY_M_LEDC_TX_C_LSB BIT_6 /* Tx Control (LSB, 88E1111 only) */
#define PHY_M_EC2_FI_IMPED BIT_6 /* Fiber Input Impedance */
#define GM_GPCR_FL_PASS BIT_6 /* Force Link Pass */
#define GMR_FS_BAD_FC BIT_6 /* Bad Flow-Control Packet */
#define GMF_RX_F_FL_OFF BIT_6 /* Rx FIFO Flush Mode Off */
#define GMF_CLI_TX_FU BIT_6 /* Clear IRQ Tx FIFO Underrun */
#define GMC_H_BURST_OFF BIT_6 /* Half Duplex Burst Mode Off */
#define PCI_EXT_PATCH_2 BIT_6
#define PCI_GAT_CLKRUN_REQ_REL BIT_6 /* CLKRUN Not Requested */
#define CS_CL_SW_IRQ BIT_6 /* Clear IRQ SW Request */
#define PC_VAUX_DIS BIT_6 /* Switch VAUX Disable */
#define Y2_IS_PTP_TIST BIT_6 /* PTP TIme Stamp (Yukon Optima) */
#define Y2_CLK_GAT_LNK2_DIS BIT_6 /* Disable clock gating Link 2 */
#define TST_FRC_DPERR_MW BIT_6 /* force DATAPERR on MST WR */
#define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6
#define Q81_CTL_FUNC_SPECIFIC_EPC_I BIT_6
#define Q81_CTL_CONFIG_LCQ BIT_6
#define Q81_CTL_INTRM_LSC BIT_6
#define Q81_WQ_ICB_FLAGS_LI BIT_6
#define Q81_CQ_ICB_FLAGS_LI BIT_6
#define Q81_TX_TSO_FLAGS_IPV4 BIT_6
#define Q81_TX_MAC_COMP_FLAGS_P BIT_6
#define Q81_TX_TSO_COMP_FLAGS_P BIT_6
#define Q81_RX_FLAGS1_T BIT_6