BIT_4
#define I2C_BURST_LEN BIT_4 /* Burst Len, 1/4 bytes */
#define TXA_DIS_ALLOC BIT_4 /* Disable alloc of free bandwidth */
#define TXA_INT_T_OFF BIT_4 /* Tx Arb Interval Timer Test Off */
#define BMU_FIFO_RST BIT_4 /* Reset FIFO */
#define RB_WP_INC BIT_4 /* Write Pointer Increment */
#define RB_DIS_STFWD BIT_4 /* Disable Store & Forward */
#define WOL_CTL_DIS_LINK_CHG_UNIT BIT_4
#define PHY_M_PC_DIS_125CLK BIT_4 /* Disable 125 CLK */
#define PHY_M_PS_ENDET_STAT BIT_4 /* Energy Detect Status (1=act) */
#define PHY_M_IS_END_CHANGE BIT_4 /* Energy Detect Changed */
#define PHY_M_EC2_FO_M_CLK BIT_4 /* Fiber Mode Clock Enable */
#define PHY_M_DTE_POW_STAT BIT_4 /* DTE Power Status (88E1111 only) */
#define GM_GPSR_GIG_SPEED BIT_4 /* Gigabit Speed (1 = 1000 Mbps) */
#define GM_GPCR_FC_RX_DIS BIT_4 /* Disable Rx Flow-Control Mode */
#define GM_SMI_CT_RD_VAL BIT_4 /* Read Valid (Read completed) */
#define GM_PAR_MIB_TST BIT_4 /* MIB Load Counter (Test Mode) */
#define GMR_FS_LONG_ERR BIT_4 /* Too Long Packet */
#define GMF_CLI_RX_FC BIT_4 /* Clear IRQ Rx Frame Complete */
#define GMF_CLI_TX_PE BIT_4 /* Clear IRQ Tx Parity Error */
#define PC_POLL_RQ BIT_4 /* Poll Request Start */
#define Y2_ASF_OS_PRES BIT_4 /* ASF operation system present */
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE1 BIT_4
#define Y2_ASF_HCU_CCSR_CPU_CLK_DIVIDE_MSK (BIT_4 | BIT_3) /* CPU Clock Divide */
#define SC_STAT_CLR_IRQ BIT_4 /* Status Burst IRQ clear */
#define GMC_F_LOOPB_OFF BIT_4 /* FIFO Loopback Off */
#define GM_IS_TX_CO_OV BIT_4 /* Transmit Counter Overflow IRQ */
#define PCI_EXT_PATCH_0 BIT_4
#define PCI_ASPM_FORCE_CLKREQ_ENA BIT_4 /* Force CLKREQ Enable (A1b only) */
#define PCI_GAT_PME_DE_ASSERTED BIT_4 /* PME De-Asserted */
#define PEX_DC_EN_REL_ORD BIT_4 /* Enable Relaxed Ordering */
#define PEX_DATA_LINK_P BIT_4 /* Data Link Protocol Error */
#define CS_STOP_MAST BIT_4 /* Command Bit to stop the master */
#define PC_VCC_DIS BIT_4 /* Switch VCC Disable */
#define Y2_IS_IRQ_PHY1 BIT_4 /* Interrupt from PHY 1 */
#define Y2_IS_PAR_WR1 BIT_4 /* Write RAM parity error interrupt */
#define Y2_PCI_CLK_LNK2_DIS BIT_4 /* Disable PCI clock Link 2 */
#define TST_FRC_DPERR_TW BIT_4 /* force DATAPERR on TRG WR */
#define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4
#define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4
#define Q81_COMPQ_VALID_V BIT_4
#define Q81_CTL_SYSTEM_ENABLE_DWC BIT_4
#define Q81_CTL_STATUS_PI0 BIT_4
#define Q81_CTL_INTRM_LH1 BIT_4
#define Q81_CTL_NIC_RCVC_R4T BIT_4
#define Q81_CTL_RD_MCAST_HASH_MATCH BIT_4
#define Q81_WQ_ICB_VALID BIT_4
#define Q81_WQ_ICB_FLAGS_LC BIT_4
#define Q81_CQ_ICB_FLAGS_LS BIT_4
#define Q81_CQ_ICB_VALID BIT_4
#define Q81_TX_MAC_COMP_FLAGS_S BIT_4
#define Q81_TX_TSO_COMP_FLAGS_S BIT_4
#define Q81_RX_FLAGS0_IE BIT_4
#define Q81_WRKQ_VALID_V BIT_4