BIT_31
#define I2C_FLAG BIT_31 /* Start read/write if WR */
#define PEX_RD_ACCESS BIT_31 /* Access Mode Read = 1, Write = 0 */
#define BMU_IDLE BIT_31 /* BMU Idle State */
#define F_TX_CHK_AUTO_OFF BIT_31 /* Tx checksum auto-calc Off(Yukon EX)*/
#define TX_STFW_DIS BIT_31 /* Disable Store & Forward (Yukon-EC Ultra) */
#define BMU_OWN BIT_31 /* OWN bit: 0=host/1=BMU */
#define PCI_Y2_PIG_ENA BIT_31 /* Enable Plug-in-Go (YUKON-2) */
#define PCI_OS_PCI64B BIT_31 /* Conventional PCI 64 bits Bus */
#define PCI_CTL_DIV_CORE_CLK_ENA BIT_31 /* Divide Core Clock Enable */
#define Y2_IS_HW_ERR BIT_31 /* Interrupt HW Error */
#define GLB_GPIO_CLK_DEB_ENA BIT_31 /* Clock Debug Enable */
#define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31
#define Q81_XG_SERDES_ADDR_RDY BIT_31
#define Q81_XGMAC_ADDR_RDY BIT_31
#define Q81_CTL_PROC_ADDR_RDY BIT_31
#define Q81_CTL_FLASH_ADDR_RDY BIT_31
#define Q81_CTL_MAC_PROTO_AI_MW BIT_31
#define Q81_CTL_RI_MW BIT_31
#define Q81_CTL_RD_RSS_MATCH BIT_31