sys/dev/msk/if_mskreg.h

1050

#define PEX_DB_ACCESS BIT_30 /* Access to debug register */

sys/dev/msk/if_mskreg.h

1097

#define BMU_RX_TCP_PKT BIT_30 /* Rx TCP Packet (when RSS Hash enabled) */

sys/dev/msk/if_mskreg.h

1130

#define F_TX_CHK_AUTO_ON BIT_30 /* Tx checksum auto-calc On(Yukon EX)*/

sys/dev/msk/if_mskreg.h

1984

#define TX_STFW_ENA BIT_30 /* Enable Store & Forward (Yukon-EC Ultra) */

sys/dev/msk/if_mskreg.h

2296

#define BMU_STF BIT_30 /* Start of Frame */

sys/dev/msk/if_mskreg.h

263

#define PCI_Y2_DLL_DIS BIT_30 /* Disable PCI DLL (YUKON-2) */

sys/dev/msk/if_mskreg.h

312

#define PCI_OS_PCIX BIT_30 /* PCI-X Bus */

sys/dev/msk/if_mskreg.h

345

#define PCI_CTL_SRESET_VMAIN_AV BIT_30 /* Soft Reset for Vmain_av De-Glitch */

sys/dev/msk/if_mskreg.h

828

#define Y2_IS_STAT_BMU BIT_30 /* Status BMU Interrupt */

sys/dev/qlxgbe/ql_hw.h

447

#define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30

sys/dev/qlxge/qls_dump.c

539

#define Q81_XG_SERDES_ADDR_READ BIT_30

sys/dev/qlxge/qls_dump.c

570

#define Q81_XGMAC_ADDR_R BIT_30

sys/dev/qlxge/qls_hw.h

173

#define Q81_CTL_PROC_ADDR_READ BIT_30

sys/dev/qlxge/qls_hw.h

362

#define Q81_CTL_FLASH_ADDR_R BIT_30

sys/dev/qlxge/qls_hw.h

380

#define Q81_CTL_MAC_PROTO_AI_MR BIT_30

sys/dev/qlxge/qls_hw.h

437

#define Q81_CTL_RI_MR BIT_30

sys/dev/qlxge/qls_hw.h

495

#define Q81_CTL_RD_RSS_IPV4 BIT_30