BIT_2
#define I2C_DATA_DIR BIT_2 /* direction of I2C_DATA */
#define BSC_T_ON BIT_2 /* Test mode on */
#define TXA_STOP_RC BIT_2 /* Stop sync Rate Control */
#define TXA_LIM_T_ON BIT_2 /* Tx Arb Limit Timer Test On */
#define BMU_OP_OFF BIT_2 /* BMU Operational Off */
#define PREF_UNIT_OP_OFF BIT_2 /* prefetch unit not operational */
#define RB_PC_T_ON BIT_2 /* Packet Counter Test On */
#define RB_RP_T_ON BIT_2 /* Read Pointer Test On */
#define RB_DIS_OP_MD BIT_2 /* Disable Operation Mode */
#define WOL_CTL_DIS_MAGIC_PKT_UNIT BIT_2
#define PHY_M_PC_SQE_T_ENA BIT_2 /* SQE Test Enabled */
#define PHY_M_PS_RX_P_EN BIT_2 /* Rx Pause Enabled */
#define PHY_M_IS_DTE_CHANGE BIT_2 /* DTE Power Det. Status Changed */
#define PHY_M_EC_DTE_D_ENA BIT_2 /* DTE Detect Enable (88E1111 only) */
#define PHY_M_LEDC_DP_CTRL BIT_2 /* Duplex Control */
#define PHY_M_LEDC_DP_C_MSB BIT_2 /* Duplex Control (MSB, 88E1111 only) */
#define PHY_M_FESC_DIS_WAIT BIT_2 /* Disable TDR Waiting Period */
#define GM_GPSR_FC_RX_DIS BIT_2 /* Rx Flow-Control Mode Disabled */
#define GM_GPCR_AU_DUP_DIS BIT_2 /* Disable Auto-Update Duplex */
#define GMF_OPER_OFF BIT_2 /* Operational Mode Off */
#define GMT_ST_START BIT_2 /* Start Time Stamp Timer */
#define PC_POLL_OP_OFF BIT_2 /* Operational Mode Off */
#define Y2_ASF_RUNNING BIT_2 /* ASF system operational */
#define Y2_ASF_HCU_CCSR_OS_PRSNT BIT_2 /* ASF OS Present */
#define SC_STAT_OP_OFF BIT_2 /* Operational Mode Off */
#define GMC_PAUSE_OFF BIT_2 /* Pause Off */
#define GM_IS_TX_COMPL BIT_2 /* Frame Transmission Complete */
#define PCI_REV_DESC BIT_2 /* Reverse Desc. Bytes */
#define PCI_ASPM_A1_MODE_SELECT BIT_2 /* A1 Mode Select (A1 only) */
#define PCI_GAT_LOADER_FINISHED BIT_2 /* EPROM Loader Finished */
#define PEX_DC_EN_FAT_ER_RP BIT_2 /* Enable Fatal Error Reporting */
#define CS_MRST_SET BIT_2 /* Set Master Reset */
#define PC_VAUX_OFF BIT_2 /* Switch VAUX Off */
#define Y2_IS_CHK_RX1 BIT_2 /* Descriptor error Rx 1 */
#define Y2_IS_PAR_RX1 BIT_2 /* Parity Error Rx Queue 1 */
#define Y2_CLK_GAT_LNK1_DIS BIT_2 /* Disable clock gating Link 1 */
#define TIM_START BIT_2 /* Start Timer */
#define TIM_T_ON BIT_2 /* Test mode on */
#define TST_FRC_APERR_T BIT_2 /* force ADDRPERR on TRG */
WRITE_REG32(ha, Q8_MBOX_INT_ENABLE, BIT_2);
data = (BIT_2|BIT_1|BIT_0);
#define Q81_CTL_SYSTEM_ENABLE_MDC BIT_2
#define Q81_CTL_CONFIG_LR BIT_2
#define Q81_CTL_STATUS_PL0 BIT_2
#define Q81_CTL_INTRM_LH0 BIT_2
#define Q81_CTL_RD_MCAST_MATCH BIT_2
#define Q81_TX_MAC_VLAN_OFF_V BIT_2
#define Q81_TX_TSO_VLAN_OFF_V BIT_2
#define Q81_RX_FLAGS0_TE BIT_2