BIT_15
#define GLB_GPIO_INT_RST_D3_DIS BIT_15 /* Disable Internal Reset After D3 to D0 */
#define BMU_ENA_RX_RSS_HASH BIT_15 /* Enable Rx RSS Hash */
#define WOL_CTL_LINK_CHG_OCC BIT_15
#define PHY_M_AN_NXT_PG BIT_15 /* Request Next Page */
#define PHY_M_PC_DIS_LINK_P BIT_15 /* Disable Link Pulses */
#define PHY_M_PC_ENA_DTE_DT BIT_15 /* Enable Data Terminal Equ. (DTE) Detect */
#define PHY_M_PS_SPEED_1000 BIT_15 /* 10 = 1000 Mbps */
#define PHY_M_PS_DTE_DETECT BIT_15 /* Data Terminal Equipment (DTE) Detected */
#define PHY_M_IS_AN_ERROR BIT_15 /* Auto-Negotiation Error */
#define PHY_M_EC_ENA_BC_EXT BIT_15 /* Enable Block Carr. Ext. (88E1111 only) */
#define PHY_M_LEDC_DIS_LED BIT_15 /* Disable LED */
#define PHY_M_FC_AUTO_SEL BIT_15 /* Fiber/Copper Auto Sel. Dis. */
#define PHY_M_CABD_ENA_TEST BIT_15 /* Enable Test (Page 0) */
#define PHY_M_CABD_DIS_WAIT BIT_15 /* Disable Waiting Period (Page 1) */
#define GM_GPSR_SPEED BIT_15 /* Port Speed (1 = 100 Mbps) */
#define GM_GPCR_RMII_PH_ENA BIT_15 /* Enable RMII for PHY (Yukon-FE only) */
#define GM_TXCR_FORCE_JAM BIT_15 /* Force Jam / Flow-Control */
#define GM_RXCR_UCF_ENA BIT_15 /* Enable Unicast filtering */
#define GMC_SEC_RST BIT_15 /* MAC SEC RST */
#define GPC_ANEG_2 BIT_15 /* ANEG[2] */
#define PCI_PEX_LEGNAT BIT_15 /* PEX PM legacy/native mode (YUKON-2) */
#define PCI_FORCE_ASPM_REQUEST BIT_15 /* Force ASPM Request (A1 only) */
#define Y2_HW_WOL_ON BIT_15 /* HW WOL On (Yukon-EC Ultra A1 only) */
#define Q8_PORT_CFG_BITS_AUTONEG BIT_15
#define Q81_CTL_RESET_FUNC BIT_15
#define Q81_CTL_FUNC_SPECIFIC_FE BIT_15
#define Q81_CTL_INTRE_EN BIT_15
#define Q81_CTL_STOP_CQ_EN BIT_15
#define Q81_CTL_RD_BCAST_OR_MCAST_MATCH BIT_15
#define Q81_WQ_ICB_RSS_V BIT_15
#define Q81_RSS_ICB_FLAGS_RT6 BIT_15
#define Q81_TXB_DESC_FLAGS_E BIT_15
#define Q81_RXB_DESC_FLAGS_E BIT_15
#define Q81_TX_TSO_FLAGS_TC BIT_15
#define Q81_RX_FLAGS1_DL BIT_15
#define Q81_RX_FLAGS2_HL BIT_15