BIT_13
#define GLB_GPIO_STAT_RACE_DIS BIT_13 /* Status Race Disable */
#define BMU_ENA_RX_CHKSUM BIT_13 /* Enable Rx TCP/IP Checksum Check */
#define BMU_TX_IPIDINCR_ON BIT_13 /* Enable IP ID Increment */
#define WOL_CTL_PATTERN_OCC BIT_13
#define PHY_M_AN_RF BIT_13 /* Remote Fault */
#define PHY_M_PC_DIS_NLP_CK BIT_13 /* Disable Normal Link Puls (NLP) Check */
#define PHY_M_PS_FULL_DUP BIT_13 /* Full Duplex */
#define PHY_M_IS_DUP_CHANGE BIT_13 /* Duplex Mode Changed */
#define PHY_M_FC_RESOLUTION BIT_13 /* Fiber/Copper Resolution */
#define GM_GPSR_FC_TX_DIS BIT_13 /* Tx Flow-Control Mode Disabled */
#define GM_GPCR_FC_TX_DIS BIT_13 /* Disable Tx Flow-Control Mode */
#define GM_TXCR_PAD_DIS BIT_13 /* Disable padding of packets */
#define GM_RXCR_CRC_DIS BIT_13 /* Remove 4-byte CRC */
#define GMR_FS_VLAN BIT_13 /* VLAN Packet */
#define GMF_WP_TST_OFF BIT_13 /* Write Pointer Test Off */
#define GMC_BYP_MACSECRX_ON BIT_13 /* Bypass MAC SEC RX */
#define GPC_ENA_PAUSE BIT_13 /* Enable Pause (SYM_OR_REM) */
#define PCI_DIS_MRL BIT_13 /* Disable Mem Read Line */
#define PCI_ASPM_INT_FIFO_EMPTY BIT_13 /* Internal FIFO Empty (A1 only) */
#define PEX_FLOW_CTRL_P BIT_13 /* Flow Control Protocol Error */
#define Y2_ASF_ENABLE BIT_13 /* ASF Unit Enable (YUKON-2 only) */
#define Y2_IS_PAR_RD2 BIT_13 /* Read RAM parity error interrupt */
#define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13
#define Q81_CTL_FUNC_SPECIFIC_STE BIT_13
#define Q81_CTL_INTRE_IHD BIT_13
#define Q81_CTL_RD_SKIP_ETHERTYPE_1 BIT_13
#define Q81_RSS_ICB_FLAGS_RT4 BIT_13
#define Q81_TX_TSO_FLAGS_LSO BIT_13
#define Q81_RX_FLAGS1_IH BIT_13
#define Q81_RX_FLAGS2_HV BIT_13