BIT_12
#define BMU_DIS_RX_CHKSUM BIT_12 /* Disable Rx TCP/IP Checksum Check */
#define BMU_TX_IPIDINCR_OFF BIT_12 /* Disable IP ID Increment */
#define WOL_CTL_CLEAR_RESULT BIT_12
#define PHY_M_1000C_MSE BIT_12 /* Manual Master/Slave Enable */
#define PHY_M_PC_ENA_LIP_NP BIT_12 /* Enable Link Partner Next Page Reg. */
#define PHY_M_PS_PAGE_REC BIT_12 /* Page Received */
#define PHY_M_IS_AN_PR BIT_12 /* Page Received */
#define PHY_M_EC_DIS_LINK_P BIT_12 /* Disable Link Pulses (88E1111 only) */
#define PHY_M_SER_IF_AN_BP BIT_12 /* Ser. IF AN Bypass Enable */
#define GM_GPSR_LINK_UP BIT_12 /* Link Up Status */
#define GM_GPCR_TX_ENA BIT_12 /* Enable Transmit */
#define GM_RXCR_PASS_FC BIT_12 /* Pass FC packets to FIFO (Yukon-1 only) */
#define GMR_FS_JABBER BIT_12 /* Jabber Packet */
#define GMF_WP_STEP BIT_12 /* Write Pointer Step/Increment */
#define GMC_BYP_MACSECRX_OFF BIT_12 /* Bypass MAC SEC RX Off */
#define GPC_PHYADDR_4 BIT_12 /* Bit 4 of Phy Addr */
#define PCI_DIS_MRM BIT_12 /* Disable Mem Read Multiple */
#define PCI_ASPM_CLKRUN_REQUEST BIT_12 /* CLKRUN Request (A1 only) */
#define PEX_LS_SLOT_CLK_CFG BIT_12 /* Slot Clock Config */
#define PEX_POIS_TLP BIT_12 /* Poisoned TLP */
#define Y2_ASF_DISABLE BIT_12 /* ASF Unit Disable (YUKON-2 only) */
#define Y2_IS_IRQ_PHY2 BIT_12 /* Interrupt from PHY 2 */
#define Y2_IS_PAR_WR2 BIT_12 /* Write RAM parity error interrupt */
#define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12
#define Q81_CTL_FUNC_SPECIFIC_DSB BIT_12
#define Q81_CTL_STATUS_NFE BIT_12
#define Q81_CTL_RD_VLAN_FILTER_PASS BIT_12
#define Q81_RSS_ICB_FLAGS_RI4 BIT_12
#define Q81_RX_FLAGS1_V6 BIT_12