BIT_1
#define I2C_DATA BIT_1 /* I2C Data Port */
#define BSC_START BIT_1 /* Start Blink Source Counter */
#define BSC_T_OFF BIT_1 /* Test mode off */
#define RI_RST_CLR BIT_1 /* Clear RAM Interface Reset */
#define TXA_ENA_ARB BIT_1 /* Enable Tx Arbiter */
#define TXA_LIM_T_OFF BIT_1 /* Tx Arb Limit Timer Test Off */
#define BMU_RST_CLR BIT_1 /* Clear BMU Reset (Enable) */
#define PREF_UNIT_RST_CLR BIT_1 /* Clear Prefetch Unit Reset */
#define RB_PC_T_OFF BIT_1 /* Packet Counter Test Off */
#define RB_RP_T_OFF BIT_1 /* Read Pointer Test Off */
#define RB_RST_CLR BIT_1 /* Clear RAM Buf STM Reset */
#define WOL_CTL_ENA_PATTERN_UNIT BIT_1
#define PHY_M_PC_POL_R_DIS BIT_1 /* Polarity Reversal Disabled */
#define PHY_M_PS_POL_REV BIT_1 /* Polarity Reversed */
#define PHY_M_IS_POL_CHANGE BIT_1 /* Polarity Changed */
#define PHY_M_EC_TX_TIM_CT BIT_1 /* RGMII Tx Timing Control */
#define PHY_M_LEDC_RX_CTRL BIT_1 /* Rx Activity / Link */
#define PHY_M_FESC_ENA_MCLK BIT_1 /* Enable MAC Rx Clock in sleep mode */
#define GM_GPCR_AU_FCT_DIS BIT_1 /* Disable Auto-Update Flow-C. */
#define GMR_FS_CRC_ERR BIT_1 /* CRC Error */
#define GMF_RST_CLR BIT_1 /* Clear GMAC FIFO Reset */
#define GMT_ST_STOP BIT_1 /* Stop Time Stamp Timer */
#define PC_POLL_RST_CLR BIT_1 /* Clear Polling Unit Reset (Enable) */
#define Y2_ASF_CLR_HSTI BIT_1 /* Clear ASF IRQ */
#define Y2_ASF_HCU_CCSR_ASF_HALTED BIT_1
#define Y2_ASF_CLR_ASFI BIT_1 /* Clear host IRQ */
#define SC_STAT_RST_CLR BIT_1 /* Clear Status Unit Reset (Enable) */
#define GMC_RST_CLR BIT_1 /* Clear GMAC Reset */
#define GPC_RST_CLR BIT_1 /* Clear GPHY Reset */
#define GM_IS_RX_FF_OR BIT_1 /* Receive FIFO Overrun */
#define GMLC_RST_CLR BIT_1 /* Clear GMAC Link Reset */
#define PCI_CLK_GATE_PEX_UNIT_ENA BIT_1 /* Enable Gate PEX Unit Clock */
#define PCI_GAT_PCIE_RX_EL_IDLE BIT_1 /* PCIe Rx Electrical Idle State */
#define PCI_CF1_ENA_TXBMU_RD_IDLE BIT_1 /* Enable TX BMU Read IDLE for ASPM */
#define PEX_DC_EN_NFA_ER_RP BIT_1 /* Enable Non-Fatal Error Reporting */
#define CS_RST_CLR BIT_1 /* Clear Software Reset */
#define LED_STAT_ON BIT_1 /* Status LED On */
#define PC_VCC_ON BIT_1 /* Switch VCC On */
#define Y2_IS_CHK_TXS1 BIT_1 /* Descriptor error TXS 1 */
#define Y2_IS_TCP_TXS1 BIT_1 /* TCP length mismatch sync Tx queue IRQ */
#define CFG_DIS_M2_CLK BIT_1 /* Disable Clock for 2nd MAC */
#define Y2_COR_CLK_LNK1_DIS BIT_1 /* Disable Core clock Link 1 */
#define CFG_LINK_2_AVAIL BIT_1 /* Link 2 available */
#define Y2_CLK_DIV_ENA BIT_1 /* Enable Core Clock Division */
#define TIM_STOP BIT_1 /* Stop Timer */
#define TIM_T_OFF BIT_1 /* Test mode off */
#define DPT_START BIT_1 /* Start Descriptor Poll Timer */
#define TST_CFG_WRITE_ON BIT_1 /* Enable Config Reg WR */
while (!((val = READ_OFFSET32(ha, Q8_ROM_STATUS)) & BIT_1)) {
if (val & BIT_1)
data = BIT_1;
data = (BIT_2|BIT_1|BIT_0);
data = (BIT_1|BIT_0);
#define Q81_CTL_SYSTEM_ENABLE_FAE BIT_1
#define Q81_CTL_CONFIG_DRQ BIT_1
#define Q81_CTL_STATUS_PI BIT_1
#define Q81_CTL_INTRM_HL0 BIT_1
#define Q81_CTL_RD_MCAST BIT_1
#define Q81_RXB_DESC_BADDR_LO_S BIT_1
#define Q81_TX_MAC_FLAGS_I BIT_1
#define Q81_TX_MAC_VLAN_OFF_DFP BIT_1
#define Q81_TX_TSO_FLAGS_I BIT_1
#define Q81_TX_TSO_VLAN_OFF_DFP BIT_1
#define Q81_TX_MAC_COMP_FLAGS_I BIT_1
#define Q81_TX_TSO_COMP_FLAGS_I BIT_1
#define Q81_SYS_COMP_FLAGS_I BIT_1
#define Q81_RX_FLAGS0_I BIT_1
#define Q81_RX_FLAGS1_V BIT_1
re_clear_mac_ocp_bit(sc, 0xEA84, (BIT_1 | BIT_0));
re_set_mac_ocp_bit(sc, 0xEA84, (BIT_1 | BIT_0));