BHND_PMU_WRITE_4
BHND_PMU_WRITE_4((_sc), (_reg), \
BHND_PMU_WRITE_4((_sc), (_reg), \
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, updt->resnum);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, updt->updown);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_UPDN_TIMER, val);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_DEP_MASK,
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_DEP_MASK, val);
BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask);
BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask);
BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmu_ctrl);
BHND_PMU_WRITE_4(sc, BHND_PMU1_PLL0_PLLCTL4, plldata);
BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pmuctrl);
BHND_PMU_WRITE_4(sc, BHND_PMU_MAX_RES_MASK, max_mask);
BHND_PMU_WRITE_4(sc, BHND_PMU_MIN_RES_MASK, min_mask);
BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
BHND_PMU_WRITE_4(sc, BHND_PMU_PLL_CONTROL_ADDR,
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, rsrc);
BHND_PMU_WRITE_4(sc, BHND_PMU_RES_TABLE_SEL, i);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 1);
BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 0);
BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val);
BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_ADDR, 1);
BHND_PMU_WRITE_4(sc, BHND_PMU_REG_CONTROL_DATA, val);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 0);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_DATA, val);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 1);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_DATA, val);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 0);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_ADDR, 1);
BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 1U <<
BHND_PMU_WRITE_4(sc, BHND_PMU_XTALFREQ, 0);
BHND_PMU_WRITE_4(sc, BHND_PMU_CTRL, pctrl);