BHND_PMU_READ_4
BHND_PMU_READ_4((_sc), (_reg)) & (_val))
BHND_PMU_READ_4((_sc), (_reg)) | (_val))
depend_mask = BHND_PMU_READ_4(sc,
query->caps = BHND_PMU_READ_4(query, BHND_PMU_CAP);
xf = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);
pmu_ctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);
pmu_ctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);
xf = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);
pmuctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);
pmuctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);
min_mask = BHND_PMU_READ_4(sc, BHND_PMU_MIN_RES_MASK);
max_mask = BHND_PMU_READ_4(sc, BHND_PMU_MIN_RES_MASK);
BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR);
tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA);
BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR);
tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA);
BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR);
tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA);
BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_ADDR);
tmp = BHND_PMU_READ_4(sc, BHND_PMU_PLL_CONTROL_DATA);
start = BHND_PMU_READ_4(sc, BHND_PMU_TIMER);
end = BHND_PMU_READ_4(sc, BHND_PMU_TIMER);
up = BHND_PMU_READ_4(sc, BHND_PMU_RES_UPDN_TIMER);
deps |= BHND_PMU_READ_4(sc, BHND_PMU_RES_DEP_MASK);
state = BHND_PMU_READ_4(sc, BHND_PMU_RES_STATE);
val = BHND_PMU_READ_4(sc, BHND_PMU_REG_CONTROL_DATA);
val = BHND_PMU_READ_4(sc, BHND_PMU_REG_CONTROL_DATA);
val = BHND_PMU_READ_4(sc, BHND_PMU_CHIP_CONTROL_DATA);
val = BHND_PMU_READ_4(sc, BHND_PMU_CHIP_CONTROL_DATA);
if ((BHND_PMU_READ_4(sc, BHND_PMU_RES_STATE) & otp_res) == 0)
pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST);
pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST);
pmu_st = BHND_PMU_READ_4(sc, BHND_PMU_ST);
ilp_ctr = BHND_PMU_READ_4(sc, BHND_PMU_XTALFREQ);
pctrl = BHND_PMU_READ_4(sc, BHND_PMU_CTRL);