BHND_PMU_CHIP_CONTROL_DATA
BHND_PMU_AND_4(sc, BHND_PMU_CHIP_CONTROL_DATA, ~0x04);
BHND_PMU_AND_4(sc, BHND_PMU_CHIP_CONTROL_DATA, 0x04);
val = BHND_PMU_READ_4(sc, BHND_PMU_CHIP_CONTROL_DATA);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_DATA, val);
val = BHND_PMU_READ_4(sc, BHND_PMU_CHIP_CONTROL_DATA);
BHND_PMU_WRITE_4(sc, BHND_PMU_CHIP_CONTROL_DATA, val);
BHND_PMU_OR_4(sc, BHND_PMU_CHIP_CONTROL_DATA, (0x01 << 29));
BHND_PMU_AND_4(sc, BHND_PMU_CHIP_CONTROL_DATA, ~0x04);