sys/dev/qlnx/qlnxe/ecore_cxt.c

1502

STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1515

STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1527

STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1578

STORE_RT_REG(p_hwfn, rt_type_offset_arr[i],

sys/dev/qlnx/qlnxe/ecore_cxt.c

1588

STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i],

sys/dev/qlnx/qlnxe/ecore_cxt.c

1622

STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));

sys/dev/qlnx/qlnxe/ecore_cxt.c

1632

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1635

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1638

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1641

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1644

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1647

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1650

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1653

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1656

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1659

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1662

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1665

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1673

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1674

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1676

STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1677

STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1687

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1690

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1693

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1708

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1711

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1719

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1722

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1725

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1733

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1736

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1739

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1747

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1750

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1753

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1822

STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1823

STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1890

STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_cxt.c

1936

STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);

sys/dev/qlnx/qlnxe/ecore_cxt.c

1945

STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);

sys/dev/qlnx/qlnxe/ecore_dev.c

2951

STORE_RT_REG(p_hwfn, PGLUE_REG_B_CACHE_LINE_SIZE_RT_OFFSET, val);

sys/dev/qlnx/qlnxe/ecore_dev.c

2953

STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_WR_RT_OFFSET, val);

sys/dev/qlnx/qlnxe/ecore_dev.c

2954

STORE_RT_REG(p_hwfn, PSWRQ2_REG_DRAM_ALIGN_RD_RT_OFFSET, val);

sys/dev/qlnx/qlnxe/ecore_dev.c

3428

STORE_RT_REG(p_hwfn, NIG_REG_BRB_GATE_DNTFWD_PORT_RT_OFFSET, 0);

sys/dev/qlnx/qlnxe/ecore_dev.c

3504

STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_EN_RT_OFFSET, 1);

sys/dev/qlnx/qlnxe/ecore_dev.c

3505

STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_TAG_VALUE_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3510

STORE_RT_REG(p_hwfn, NIG_REG_LLH_FUNC_FILTER_HDR_SEL_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3517

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_dev.c

3522

STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_TCP_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3524

STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_FCOE_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3526

STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_ROCE_RT_OFFSET, 0);

sys/dev/qlnx/qlnxe/ecore_dev.c

3812

STORE_RT_REG(p_hwfn, PRS_REG_TAG_ETHERTYPE_0_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3814

STORE_RT_REG(p_hwfn, NIG_REG_TAG_ETHERTYPE_0_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3816

STORE_RT_REG(p_hwfn, PBF_REG_TAG_ETHERTYPE_0_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_dev.c

3818

STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET,

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1263

STORE_RT_REG(p_hwfn, DORQ_REG_TAG1_ETHERTYPE_RT_OFFSET, ethType);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1595

STORE_RT_REG(p_hwfn, PGLUE_REG_B_MSDM_VF_SHIFT_B_RT_OFFSET, msdm_vf_size_log);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

1596

STORE_RT_REG(p_hwfn, PGLUE_REG_B_MSDM_OFFSET_MASK_B_RT_OFFSET, msdm_vf_offset_mask);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

173

#define QM_INIT_TX_PQ_MAP(p_hwfn, map, chip, pq_id, rl_valid, vp_pq_id, rl_id, ext_voq, wrr) OSAL_MEMSET(&map, 0, sizeof(map)); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_PQ_VALID, 1); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_VALID, rl_valid); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VP_PQ_ID, vp_pq_id); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_RL_ID, rl_id); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_VOQ, ext_voq); SET_FIELD(map.reg, QM_RF_PQ_MAP_##chip##_WRR_WEIGHT_GROUP, wrr); STORE_RT_REG(p_hwfn, QM_REG_TXPQMAP_RT_OFFSET + pq_id, *((u32 *)&map))

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

197

STORE_RT_REG(p_hwfn, QM_REG_RLPFENABLE_RT_OFFSET, pf_rl_en ? 1 : 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

203

STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_RT_OFFSET, (u32)voq_bit_mask);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

206

STORE_RT_REG(p_hwfn, QM_REG_RLPFVOQENABLE_MSB_RT_OFFSET, (u32)(voq_bit_mask >> 32));

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

210

STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIOD_RT_OFFSET, QM_RL_PERIOD_CLK_25M);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

211

STORE_RT_REG(p_hwfn, QM_REG_RLPFPERIODTIMER_RT_OFFSET, QM_RL_PERIOD_CLK_25M);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

215

STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFRL_RT_OFFSET, QM_PF_RL_UPPER_BOUND);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

223

STORE_RT_REG(p_hwfn, QM_REG_WFQPFENABLE_RT_OFFSET, pf_wfq_en ? 1 : 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

227

STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRPFWFQ_RT_OFFSET, QM_WFQ_UPPER_BOUND);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

234

STORE_RT_REG(p_hwfn, QM_REG_RLGLBLENABLE_RT_OFFSET, vport_rl_en ? 1 : 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

237

STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIOD_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

238

STORE_RT_REG(p_hwfn, QM_REG_RLGLBLPERIODTIMER_0_RT_OFFSET, QM_RL_PERIOD_CLK_25M);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

242

STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRGLBLRL_RT_OFFSET, QM_VP_RL_BYPASS_THRESH_SPEED);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

250

STORE_RT_REG(p_hwfn, QM_REG_WFQVPENABLE_RT_OFFSET, vport_wfq_en ? 1 : 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

254

STORE_RT_REG(p_hwfn, QM_REG_AFULLQMBYPTHRVPWFQ_RT_OFFSET, QM_WFQ_UPPER_BOUND);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

269

STORE_RT_REG(p_hwfn, QM_REG_VOQCRDLINE_RT_OFFSET + ext_voq, qm_line_crd);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

270

STORE_RT_REG(p_hwfn, QM_REG_VOQINITCRDLINE_RT_OFFSET + ext_voq, qm_line_crd);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

284

STORE_RT_REG(p_hwfn, PBF_CMDQ_LINES_RT_OFFSET(ext_voq), 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

371

STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq), phys_blocks);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

377

STORE_RT_REG(p_hwfn, PBF_BTB_GUARANTEED_RT_OFFSET(ext_voq), pure_lb_blocks);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

415

STORE_RT_REG(p_hwfn, QM_REG_PQTX2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

418

STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_0_RT_OFFSET, QM_PQ_SIZE_256B(num_pf_cids));

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

419

STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_1_RT_OFFSET, QM_PQ_SIZE_256B(num_vf_cids));

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

443

STORE_RT_REG(p_hwfn, QM_REG_WFQVPMAP_RT_OFFSET + first_tx_pq_id, map_val);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

461

STORE_RT_REG(p_hwfn, QM_REG_BASEADDRTXPQ_RT_OFFSET + pq_id, mem_addr_4kb);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

466

STORE_RT_REG(p_hwfn, QM_REG_PTRTBLTX_RT_OFFSET + (pq_id * 2) + j, 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

489

STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZETXSEL_0_RT_OFFSET + i, tx_pq_vf_mask[i]);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

512

STORE_RT_REG(p_hwfn, QM_REG_PQOTHER2PF_0_RT_OFFSET + pq_group, (u32)(pf_id));

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

515

STORE_RT_REG(p_hwfn, QM_REG_MAXPQSIZE_2_RT_OFFSET, QM_PQ_SIZE_256B(pq_size));

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

519

STORE_RT_REG(p_hwfn, QM_REG_BASEADDROTHERPQ_RT_OFFSET + pq_id, mem_addr_4kb);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

524

STORE_RT_REG(p_hwfn, QM_REG_PTRTBLOTHER_RT_OFFSET + (pq_id * 2) + j, 0);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

559

STORE_RT_REG(p_hwfn, QM_REG_WFQPFUPPERBOUND_RT_OFFSET + pf_id, QM_WFQ_UPPER_BOUND | (u32)QM_WFQ_CRD_REG_SIGN_BIT);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

560

STORE_RT_REG(p_hwfn, QM_REG_WFQPFWEIGHT_RT_OFFSET + pf_id, inc_val);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

580

STORE_RT_REG(p_hwfn, QM_REG_RLPFCRD_RT_OFFSET + pf_id, (u32)QM_RL_CRD_REG_SIGN_BIT);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

581

STORE_RT_REG(p_hwfn, QM_REG_RLPFUPPERBOUND_RT_OFFSET + pf_id, QM_PF_RL_UPPER_BOUND | (u32)QM_RL_CRD_REG_SIGN_BIT);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

582

STORE_RT_REG(p_hwfn, QM_REG_RLPFINCVAL_RT_OFFSET + pf_id, inc_val);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

613

STORE_RT_REG(p_hwfn, QM_REG_WFQVPCRD_RT_OFFSET + vport_pq_id, (u32)QM_WFQ_CRD_REG_SIGN_BIT);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

614

STORE_RT_REG(p_hwfn, QM_REG_WFQVPWEIGHT_RT_OFFSET + vport_pq_id, inc_val);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

647

STORE_RT_REG(p_hwfn, QM_REG_RLGLBLCRD_RT_OFFSET + vport_id, (u32)QM_RL_CRD_REG_SIGN_BIT);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

648

STORE_RT_REG(p_hwfn, QM_REG_RLGLBLUPPERBOUND_RT_OFFSET + vport_id, QM_VP_RL_UPPER_BOUND(link_speed) | (u32)QM_RL_CRD_REG_SIGN_BIT);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

649

STORE_RT_REG(p_hwfn, QM_REG_RLGLBLINCVAL_RT_OFFSET + vport_id, inc_val);

sys/dev/qlnx/qlnxe/ecore_init_fw_funcs.c

725

STORE_RT_REG(p_hwfn, QM_REG_AFULLOPRTNSTCCRDMASK_RT_OFFSET, mask);

sys/dev/qlnx/qlnxe/ecore_int.c

1513

STORE_RT_REG(p_hwfn,

sys/dev/qlnx/qlnxe/ecore_int.c

2521

STORE_RT_REG(p_hwfn, IGU_REG_PF_CONFIGURATION_RT_OFFSET, igu_pf_conf);

sys/dev/qlnx/qlnxe/ecore_sriov.c

921

STORE_RT_REG(p_hwfn, IGU_REG_VF_CONFIGURATION_RT_OFFSET, igu_vf_conf);