sys/dev/ste/if_ste.c

1579

CSR_WRITE_2(sc, STE_MACCTL1, 0);

sys/dev/ste/if_ste.c

1580

STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_TX_ENABLE);

sys/dev/ste/if_ste.c

1581

STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_RX_ENABLE);

sys/dev/ste/if_ste.c

1584

STE_SETBIT2(sc, STE_MACCTL1, STE_MACCTL1_STATS_ENABLE);

sys/dev/ste/if_ste.c

1639

val = CSR_READ_2(sc, STE_MACCTL1);

sys/dev/ste/if_ste.c

1642

CSR_WRITE_2(sc, STE_MACCTL1, val);

sys/dev/ste/if_ste.c

1645

if ((CSR_READ_2(sc, STE_MACCTL1) & (STE_MACCTL1_TX_DISABLE |

sys/dev/ste/if_ste.c

1717

mac = CSR_READ_2(sc, STE_MACCTL1);

sys/dev/ste/if_ste.c

1719

CSR_WRITE_2(sc, STE_MACCTL1, mac);

sys/dev/ste/if_ste.c

1720

mac = CSR_READ_2(sc, STE_MACCTL1);