SSI_CLK_SEL_PLL4
reg |= (SSI_CLK_SEL_PLL4 << SSI1_CLK_SEL_S);
reg |= (SSI_CLK_SEL_PLL4 << SSI2_CLK_SEL_S);
reg |= (SSI_CLK_SEL_PLL4 << SSI3_CLK_SEL_S);