sys/powerpc/aim/aim_machdep.c

702

cache_reg = mfspr(SPR_L2CR);

sys/powerpc/aim/aim_machdep.c

705

mtspr(SPR_L2CR, cache_reg);

sys/powerpc/aim/aim_machdep.c

707

mtspr(SPR_L2CR, cache_reg | L2CR_L2HWF);

sys/powerpc/aim/aim_machdep.c

708

while (mfspr(SPR_L2CR) & L2CR_L2HWF)

sys/powerpc/aim/aim_machdep.c

712

mtspr(SPR_L2CR, cache_reg);

sys/powerpc/aim/aim_machdep.c

714

mtspr(SPR_L2CR, cache_reg | L2CR_L2I);

sys/powerpc/aim/aim_machdep.c

716

while (mfspr(SPR_L2CR) & L2CR_L2I)

sys/powerpc/aim/mp_cpudep.c

157

ccr = mfspr(SPR_L2CR);

sys/powerpc/aim/mp_cpudep.c

163

mtspr(SPR_L2CR, ccr | L2CR_L2I);

sys/powerpc/aim/mp_cpudep.c

165

ccr = mfspr(SPR_L2CR);

sys/powerpc/aim/mp_cpudep.c

168

mtspr(SPR_L2CR, l2cr_config);

sys/powerpc/aim/mp_cpudep.c

298

bsp_state[2] = mfspr(SPR_L2CR);

sys/powerpc/powerpc/cpu.c

566

if (mfspr(SPR_L2CR) & L2CR_L2E) {

sys/powerpc/powerpc/cpu.c

583

switch (mfspr(SPR_L2CR) & L2CR_L2SIZ) {

sys/powerpc/powerpc/cpu.c

594

printf("write-%s", (mfspr(SPR_L2CR) & L2CR_L2WT)

sys/powerpc/powerpc/cpu.c

596

if (mfspr(SPR_L2CR) & L2CR_L2PE)