SC_PORT
storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
int port = SC_PORT(sc);
int port = SC_PORT(sc);
SC_PORT(sc));
SC_PORT(sc)*4)) &
offsetof(struct shmem_region, validity_map[SC_PORT(sc)]);
val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
sc->link_params.port = SC_PORT(sc);
SC_PORT(sc));
SC_PORT(sc));
port = SC_PORT(sc);
val = SHMEM_RD(sc, validity_map[SC_PORT(sc)]);
sc->base_fw_ndsb = ((SC_PORT(sc) * FP_SB_MAX_E1x) + SC_L_ID(sc));
uint8_t port = SC_PORT(sc);
uint8_t port = SC_PORT(sc);
tmp->undi = after_undi ? (1 << SC_PORT(sc)) : 0;
opcode |= (SC_PORT(sc) ? DMAE_CMD_PORT_1 : DMAE_CMD_PORT_0);
uint8_t port = SC_PORT(sc);
base_addr = SC_PORT(sc) ? NIG_REG_INGRESS_BMAC1_MEM
vals->emac_addr = NIG_REG_NIG_EMAC0_EN + SC_PORT(sc)*4;
base_addr = SC_PORT(sc) ? GRCBASE_XMAC1 : GRCBASE_XMAC0;
base_addr = SC_PORT(sc) ? GRCBASE_UMAC1 : GRCBASE_UMAC0;
bxe_prev_unload_undi_inc(sc, SC_PORT(sc), 1);
(MCPR_NVM_SW_ARB_ARB_REQ_CLR1 << SC_PORT(sc)));
lfa_host_addr[SC_PORT(sc)])) {
int port = SC_PORT(sc);
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, SC_PORT(sc) ?
REG_WR(sc, (SC_PORT(sc) ? NIG_REG_LLH1_CLS_TYPE :
TM_REG_LIN0_VNIC_UC + 4*SC_PORT(sc),
TM_REG_LIN0_NUM_SCANS + 4*SC_PORT(sc),
int port = SC_PORT(sc);
int port = SC_PORT(sc);
SC_PORT(sc) * (main_mem_size * 4);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
abs_func = (n * (2 * vn + SC_PORT(sc)) + SC_PATH(sc));
int port = SC_PORT(sc);
USTORM_ETH_PAUSE_ENABLED_OFFSET(SC_PORT(sc))),
storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
storm_memset_cmng(sc, &sc->cmng, SC_PORT(sc));
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
return (fp->cl_id + SC_PORT(fp->sc) * ETH_MAX_RX_CLIENTS_E1H);
offset += USTORM_RX_PRODS_E1X_OFFSET(SC_PORT(sc), fp->cl_id);
int port = SC_PORT(sc);
#define PORT_ID(sc) SC_PORT(sc)
(SC_PORT(sc) + (vn) * \
#define INIT_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + SC_VN(sc))
#define PMF_DMAE_C(sc) ((SC_PORT(sc) * MAX_DMAE_C_PER_PORT) + E1HVN_MAX)
((SC_PORT(sc) << 23) | (SC_VN(sc) << BXE_SWCID_SHIFT) | (x))
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
uint32_t hc_addr = (HC_REG_COMMAND_REG + SC_PORT(sc)*32 +
return (2 * vn + SC_PORT(sc));
return (fp->cl_id + SC_PORT(sc) * FP_SB_MAX_E1x);
cur_query_entry->index = SC_PORT(sc);
cur_query_entry->index = SC_PORT(sc);
int /*abs*/port = SC_PORT(sc);
port = SC_PORT(sc);
int port = SC_PORT(sc);
lpi_reg = (SC_PORT(sc)) ?
nig_timer_max = SHMEM_RD(sc, port_mb[SC_PORT(sc)].stat_nig_timer);
int port = SC_PORT(sc);
int port = SC_PORT(sc);
#define ECORE_PORT_ID SC_PORT