sys/riscv/sifive/sifive_uart.c

102

uart_setreg(bas, SFUART_IRQ_ENABLE, 0);

sys/riscv/sifive/sifive_uart.c

229

uart_setreg(bas, SFUART_IRQ_ENABLE, SFUART_IRQ_ENABLE_RXWM);

sys/riscv/sifive/sifive_uart.c

248

uart_setreg(bas, SFUART_IRQ_ENABLE, 0);

sys/riscv/sifive/sifive_uart.c

368

ie = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

376

uart_setreg(bas, SFUART_IRQ_ENABLE, ie);

sys/riscv/sifive/sifive_uart.c

459

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

461

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/sifive/sifive_uart.c

482

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

484

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);

sys/riscv/sifive/sifive_uart.c

498

reg = uart_getreg(bas, SFUART_IRQ_ENABLE);

sys/riscv/sifive/sifive_uart.c

500

uart_setreg(bas, SFUART_IRQ_ENABLE, reg);