SET_PROP_U32
SET_PROP_U32(prop, 0, 256);
SET_PROP_U32(prop, 1, 64);
SET_PROP_U32(interrupts, 0, GIC_SPI);
SET_PROP_U32(interrupts, 1, intr - GIC_FIRST_SPI);
SET_PROP_U32(interrupts, 2, IRQ_TYPE_LEVEL_HIGH);
SET_PROP_U32(prop, 0, apb_pclk_phandle);
SET_PROP_U32(prop, 1, apb_pclk_phandle);
SET_PROP_U32(interrupts, 0, GIC_SPI);
SET_PROP_U32(interrupts, 1, intr - GIC_FIRST_SPI);
SET_PROP_U32(interrupts, 2, IRQ_TYPE_LEVEL_HIGH);
SET_PROP_U32(prop, 0, apb_pclk_phandle);
SET_PROP_U32(interrupts, i * 3 + 0, GIC_PPI);
SET_PROP_U32(interrupts, i * 3 + 1, irqs[i]);
SET_PROP_U32(interrupts, i * 3 + 2, IRQ_TYPE_LEVEL_LOW);
SET_PROP_U32(prop, 0, 0x01000000);
SET_PROP_U32(prop, 1, 0);
SET_PROP_U32(prop, 2, 0xdf000000);
SET_PROP_U32(prop, 3, 0);
SET_PROP_U32(prop, 4, 0xdf000000);
SET_PROP_U32(prop, 5, 0);
SET_PROP_U32(prop, 6, 0x01000000);
SET_PROP_U32(prop, 7, 0x02000000);
SET_PROP_U32(prop, 8, 0);
SET_PROP_U32(prop, 9, 0xa0000000);
SET_PROP_U32(prop, 10, 0);
SET_PROP_U32(prop, 11, 0xa0000000);
SET_PROP_U32(prop, 12, 0);
SET_PROP_U32(prop, 13, 0x3f000000);
SET_PROP_U32(prop, 0, 0); /* RID base */
SET_PROP_U32(prop, 1, gic_phandle); /* MSI parent */
SET_PROP_U32(prop, 2, 0); /* MSI base */
SET_PROP_U32(prop, 3, 0x10000); /* RID length */
SET_PROP_U32(prop, 0, 3 << 11);
SET_PROP_U32(prop, 1, 0);
SET_PROP_U32(prop, 2, 0);
SET_PROP_U32(prop, 3, 7);
SET_PROP_U32(prop, 10 * i + 0, slot << 11);
SET_PROP_U32(prop, 10 * i + 1, 0);
SET_PROP_U32(prop, 10 * i + 2, 0);
SET_PROP_U32(prop, 10 * i + 3, pin + 1);
SET_PROP_U32(prop, 10 * i + 4, gic_phandle);
SET_PROP_U32(prop, 10 * i + 5, 0);
SET_PROP_U32(prop, 10 * i + 6, 0);
SET_PROP_U32(prop, 10 * i + 7, GIC_SPI);
SET_PROP_U32(prop, 10 * i + 8, intr - GIC_FIRST_SPI);
SET_PROP_U32(prop, 10 * i + 9, IRQ_TYPE_LEVEL_HIGH);
SET_PROP_U32(prop, i * 2 + 0, intc_phandles[i]);
SET_PROP_U32(prop, i * 2 + 1, IRQ_EXTERNAL_SUPERVISOR);
SET_PROP_U32(interrupts, 0, intr);
SET_PROP_U32(interrupts, 1, IRQ_TYPE_LEVEL_HIGH);
SET_PROP_U32(prop, 0, 0x01000000);
SET_PROP_U32(prop, 1, 0);
SET_PROP_U32(prop, 2, 0xdf000000);
SET_PROP_U32(prop, 3, 0);
SET_PROP_U32(prop, 4, 0xdf000000);
SET_PROP_U32(prop, 5, 0);
SET_PROP_U32(prop, 6, 0x01000000);
SET_PROP_U32(prop, 7, 0x02000000);
SET_PROP_U32(prop, 8, 0);
SET_PROP_U32(prop, 9, 0xa0000000);
SET_PROP_U32(prop, 10, 0);
SET_PROP_U32(prop, 11, 0xa0000000);
SET_PROP_U32(prop, 12, 0);
SET_PROP_U32(prop, 13, 0x3f000000);
SET_PROP_U32(prop, 0, 0); /* RID base */
SET_PROP_U32(prop, 1, aplic_phandle); /* MSI parent */
SET_PROP_U32(prop, 2, 0); /* MSI base */
SET_PROP_U32(prop, 3, 0x10000); /* RID length */
SET_PROP_U32(prop, 0, 3 << 11);
SET_PROP_U32(prop, 1, 0);
SET_PROP_U32(prop, 2, 0);
SET_PROP_U32(prop, 3, 7);
SET_PROP_U32(prop, 10 * i + 0, slot << 11);
SET_PROP_U32(prop, 10 * i + 1, 0);
SET_PROP_U32(prop, 10 * i + 2, 0);
SET_PROP_U32(prop, 10 * i + 3, pin + 1);
SET_PROP_U32(prop, 10 * i + 4, aplic_phandle);
SET_PROP_U32(prop, 10 * i + 5, 0);
SET_PROP_U32(prop, 10 * i + 6, 0);
SET_PROP_U32(prop, 10 * i + 7, intr);
SET_PROP_U32(prop, 10 * i + 8, IRQ_TYPE_LEVEL_HIGH);