sys/dev/uart/uart_dev_imx.c

205

SETREG(bas, REG(UFCR), reg);

sys/dev/uart/uart_dev_imx.c

206

SETREG(bas, REG(UBIR), 15);

sys/dev/uart/uart_dev_imx.c

207

SETREG(bas, REG(UBMR), (baseclk / baudrate) - 1);

sys/dev/uart/uart_dev_imx.c

219

SETREG(bas, REG(UFCR), reg);

sys/dev/uart/uart_dev_imx.c

234

SETREG(bas, REG(UTXD), c);

sys/dev/uart/uart_dev_imx.c

394

SETREG(bas, REG(USR1), 0xffff);

sys/dev/uart/uart_dev_imx.c

395

SETREG(bas, REG(USR2), 0xffff);

sys/dev/uart/uart_dev_imx.c

432

SETREG(&sc->sc_bas, REG(UCR4), 0);

sys/dev/uart/uart_dev_imx.c

507

SETREG(bas, REG(USR1), usr1);

sys/dev/uart/uart_dev_imx.c

508

SETREG(bas, REG(USR2), usr2);

sys/dev/uart/uart_dev_imx.c

638

SETREG(bas, REG(UTXD), sc->sc_txbuf[i] & 0xff);

sys/dev/uart/uart_dev_imx.h

207

SETREG((_bas), (_r), GETREG((_bas), (_r)) & ~(_b))

sys/dev/uart/uart_dev_imx.h

209

SETREG((_bas), (_r), GETREG((_bas), (_r)) | (_b))

sys/dev/uart/uart_dev_lowrisc.c

110

SETREG(bas, UART_DR, c);

sys/dev/uart/uart_dev_lowrisc.c

129

SETREG(bas, UART_INT_STATUS, INT_STATUS_ACK);

sys/dev/uart/uart_dev_lowrisc.c

276

SETREG(bas, UART_INT_STATUS, INT_STATUS_ACK);

sys/dev/uart/uart_dev_lowrisc.c

334

SETREG(bas, UART_INT_STATUS, INT_STATUS_ACK);

sys/dev/uart/uart_dev_lowrisc.c

362

SETREG(bas, UART_DR, sc->sc_txbuf[i] & 0xff);

sys/dev/uart/uart_dev_msm.c

194

SETREG(bas, UART_DM_CR, UART_DM_RESET_TX);

sys/dev/uart/uart_dev_msm.c

195

SETREG(bas, UART_DM_CR, UART_DM_RESET_RX);

sys/dev/uart/uart_dev_msm.c

196

SETREG(bas, UART_DM_CR, UART_DM_RESET_ERROR_STATUS);

sys/dev/uart/uart_dev_msm.c

197

SETREG(bas, UART_DM_CR, UART_DM_RESET_BREAK_INT);

sys/dev/uart/uart_dev_msm.c

198

SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);

sys/dev/uart/uart_dev_msm.c

237

SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);

sys/dev/uart/uart_dev_msm.c

247

SETREG(bas, UART_DM_TF(0), (c & 0xff));

sys/dev/uart/uart_dev_msm.c

375

SETREG(bas, UART_DM_IMR, u->ier);

sys/dev/uart/uart_dev_msm.c

406

SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);

sys/dev/uart/uart_dev_msm.c

407

SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_ENABLE);

sys/dev/uart/uart_dev_msm.c

409

SETREG(bas, UART_DM_IMR, u->ier);

sys/dev/uart/uart_dev_msm.c

468

SETREG(bas, UART_DM_IMR, u->ier);

sys/dev/uart/uart_dev_msm.c

476

SETREG(bas, UART_DM_CR, UART_DM_STALE_EVENT_DISABLE);

sys/dev/uart/uart_dev_msm.c

477

SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);

sys/dev/uart/uart_dev_msm.c

485

SETREG(bas, UART_DM_CR, UART_DM_CLEAR_TX_READY);

sys/dev/uart/uart_dev_msm.c

489

SETREG(bas, UART_DM_IMR, u->ier);

sys/dev/uart/uart_dev_msm.c

499

SETREG(bas, UART_DM_IMR, u->ier);

sys/dev/uart/uart_dev_msm.c

541

SETREG(bas, UART_DM_CR, UART_DM_RESET_STALE_INT);

sys/dev/uart/uart_dev_msm.c

542

SETREG(bas, UART_DM_IMR, 0);

sys/dev/uart/uart_dev_msm.c

557

SETREG(bas, UART_DM_IMR, u->ier);

usr.sbin/bhyve/amd64/task_switch.c

499

SETREG(vcpu, VM_REG_GUEST_LDTR, tss->tss_ldt);

usr.sbin/bhyve/amd64/task_switch.c

523

SETREG(vcpu, VM_REG_GUEST_PDPTE0, pdpte[0]);

usr.sbin/bhyve/amd64/task_switch.c

524

SETREG(vcpu, VM_REG_GUEST_PDPTE1, pdpte[1]);

usr.sbin/bhyve/amd64/task_switch.c

525

SETREG(vcpu, VM_REG_GUEST_PDPTE2, pdpte[2]);

usr.sbin/bhyve/amd64/task_switch.c

526

SETREG(vcpu, VM_REG_GUEST_PDPTE3, pdpte[3]);

usr.sbin/bhyve/amd64/task_switch.c

528

SETREG(vcpu, VM_REG_GUEST_CR3, tss->tss_cr3);

usr.sbin/bhyve/amd64/task_switch.c

533

SETREG(vcpu, VM_REG_GUEST_RFLAGS, eflags);

usr.sbin/bhyve/amd64/task_switch.c

534

SETREG(vcpu, VM_REG_GUEST_RIP, tss->tss_eip);

usr.sbin/bhyve/amd64/task_switch.c

537

SETREG(vcpu, VM_REG_GUEST_RAX, tss->tss_eax);

usr.sbin/bhyve/amd64/task_switch.c

538

SETREG(vcpu, VM_REG_GUEST_RCX, tss->tss_ecx);

usr.sbin/bhyve/amd64/task_switch.c

539

SETREG(vcpu, VM_REG_GUEST_RDX, tss->tss_edx);

usr.sbin/bhyve/amd64/task_switch.c

540

SETREG(vcpu, VM_REG_GUEST_RBX, tss->tss_ebx);

usr.sbin/bhyve/amd64/task_switch.c

541

SETREG(vcpu, VM_REG_GUEST_RSP, tss->tss_esp);

usr.sbin/bhyve/amd64/task_switch.c

542

SETREG(vcpu, VM_REG_GUEST_RBP, tss->tss_ebp);

usr.sbin/bhyve/amd64/task_switch.c

543

SETREG(vcpu, VM_REG_GUEST_RSI, tss->tss_esi);

usr.sbin/bhyve/amd64/task_switch.c

544

SETREG(vcpu, VM_REG_GUEST_RDI, tss->tss_edi);

usr.sbin/bhyve/amd64/task_switch.c

547

SETREG(vcpu, VM_REG_GUEST_ES, tss->tss_es);

usr.sbin/bhyve/amd64/task_switch.c

548

SETREG(vcpu, VM_REG_GUEST_CS, tss->tss_cs);

usr.sbin/bhyve/amd64/task_switch.c

549

SETREG(vcpu, VM_REG_GUEST_SS, tss->tss_ss);

usr.sbin/bhyve/amd64/task_switch.c

550

SETREG(vcpu, VM_REG_GUEST_DS, tss->tss_ds);

usr.sbin/bhyve/amd64/task_switch.c

551

SETREG(vcpu, VM_REG_GUEST_FS, tss->tss_fs);

usr.sbin/bhyve/amd64/task_switch.c

552

SETREG(vcpu, VM_REG_GUEST_GS, tss->tss_gs);

usr.sbin/bhyve/amd64/task_switch.c

685

SETREG(vcpu, VM_REG_GUEST_RSP, esp);

usr.sbin/bhyve/amd64/task_switch.c

865

SETREG(vcpu, VM_REG_GUEST_TR, nt_sel);

usr.sbin/bhyve/amd64/task_switch.c

873

SETREG(vcpu, VM_REG_GUEST_CR0, cr0 | CR0_TS);