SET4
SET4(sc->pmu[phyno], PMU_IRQ_ENABLE, PMU_ULPI_BYPASS |
SET4(sc->phy_ctrl, OTG_PHY_CFG, OTG_PHY_ROUTE_OTG);
SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq));
SET4(sc, IMX_GPIO_IMR_REG, (1u << irq));
SET4(sc, IMX_GPIO_IMR_REG, (1U << irq));
SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin));
SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin));
SET4(sc, IMX_GPIO_DR_REG, (1U << pin));