SDHCI_INT_STATUS
reg = bcm_sdhci_read_4(slot->bus, slot, SDHCI_INT_STATUS) &
bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS,
bcm_sdhci_write_4(slot->bus, slot, SDHCI_INT_STATUS,
case SDHCI_INT_STATUS:
case SDHCI_INT_STATUS:
RD4(sc, SDHCI_INT_STATUS);
val32 = RD4(sc, SDHCI_INT_STATUS);
if (off == SDHCI_INT_STATUS) {
if (off == SDHCI_INT_STATUS) {
intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_RESPONSE;
intmask = RD4(sc, SDHCI_INT_STATUS) & SDHCI_INT_DATA_END;
WR4(sc, SDHCI_INT_STATUS, intmask);
bus_barrier(sc->mem_res, SDHCI_INT_STATUS, 4,
intmask = RD4(slot, SDHCI_INT_STATUS);
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_TUNEERR);
WR4(slot, SDHCI_INT_STATUS, intmask &
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_CMD_MASK);
WR4(slot, SDHCI_INT_STATUS, intmask & SDHCI_INT_DATA_MASK);
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_ACMD12ERR);
RD1(slot, SDHCI_TIMEOUT_CONTROL), RD4(slot, SDHCI_INT_STATUS));
WR4(slot, SDHCI_INT_STATUS, SDHCI_INT_BUS_POWER);
WR4(slot, SDHCI_INT_STATUS, intmask);
val32 = RD4(sc, SDHCI_INT_STATUS);