RW
if (RW) {
reg = RW(reg, R92C_EFUSE_CTRL_ADDR, sc->next_rom_addr);
reg = RW(reg, R92C_MCUFWDL_PAGE, page);
RW(reg, R92C_AFE_XTAL_CTRL_ADDR, val | val << 6));
RW(rf_ac[i], R92C_RF_AC_MODE,
reg = RW(reg, R92C_TXAGC_A_CCK1, power[RTWN_RIDX_CCK1]);
reg = RW(reg, R92C_TXAGC_A_CCK2, power[RTWN_RIDX_CCK2]);
reg = RW(reg, R92C_TXAGC_A_CCK55, power[RTWN_RIDX_CCK55]);
reg = RW(reg, R92C_TXAGC_A_CCK11, power[RTWN_RIDX_CCK11]);
reg = RW(reg, R92C_TXAGC_B_CCK1, power[RTWN_RIDX_CCK1]);
reg = RW(reg, R92C_TXAGC_B_CCK2, power[RTWN_RIDX_CCK2]);
reg = RW(reg, R92C_TXAGC_B_CCK55, power[RTWN_RIDX_CCK55]);
reg = RW(reg, R92C_TXAGC_B_CCK11, power[RTWN_RIDX_CCK11]);
RW(rs->rf_chnlbw[i], R92C_RF_CHNLBW_CHNL, chan));
RW(reg[chain], R92C_HSSI_PARAM2_READ_ADDR, addr) |
reg = RW(reg, R92C_TDECTRL_BLK_DESC_NUM, uc->tx_agg_desc_num);
RW(rs->rf_chnlbw[0], R92C_RF_CHNLBW_CHNL, chan));
RW(reg, R92E_AFE_XTAL_CTRL_ADDR, val | val << 6));
RW(val, R92C_HSSI_PARAM2_READ_ADDR, addr) &
val = RW(val, R12A_RFMOD_EXT_CHAN, ext20);
val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext20);
val = RW(val, R12A_RFMOD_EXT_CHAN, ext_chan);
val = RW(val, R12A_CCA_ON_SEC_EXT_CHAN, ext_chan);
reg = RW(reg, R12A_MAC_PHY_CRYSTALCAP, val | (val << 6));
reg = RW(reg, R21A_MAC_PHY_CRYSTALCAP, val | (val << 6));
reg = RW(reg, R92S_EFUSE_CTRL_ADDR, addr);
mode = RW & ~umask(RW);