sys/arm/nvidia/as3722.c

227

rv = RM1(sc, AS3722_IO_VOLTAGE,

sys/arm/nvidia/as3722_gpio.c

467

rv = RM1(sc, AS3722_GPIO_SIGNAL_OUT, (1 << pin), (tmp << pin));

sys/arm/nvidia/as3722_gpio.c

519

rv = RM1(sc, AS3722_GPIO_SIGNAL_OUT, (1 << pin), tmp);

sys/arm/nvidia/as3722_regulators.c

405

rv = RM1(sc->base_sc, sc->def->volt_reg,

sys/arm/nvidia/as3722_regulators.c

431

rv = RM1(sc->base_sc, sc->def->ext_enable_reg,

sys/arm/nvidia/as3722_regulators.c

441

rv = RM1(sc->base_sc, sc->def->enable_reg,

sys/arm/nvidia/as3722_regulators.c

451

rv = RM1(sc->base_sc, sc->def->enable_reg,

sys/arm/nvidia/as3722_regulators.c

473

rv = RM1(sc->base_sc, sc->def->volt_reg,

sys/arm/nvidia/as3722_rtc.c

102

rv = RM1(sc, AS3722_RTC_CONTROL,

sys/arm64/nvidia/tegra210/max77620.c

317

rv = RM1(sc, MAX77620_REG_FPS_CFG0 + i, mask, val);

sys/arm64/nvidia/tegra210/max77620.c

325

rv = RM1(sc, MAX77620_REG_INTENLBT, 0x81, 0x81);

sys/arm64/nvidia/tegra210/max77620.c

326

rv = RM1(sc, MAX77620_REG_IRQTOPM, 0x81, 0x81);

sys/arm64/nvidia/tegra210/max77620_gpio.c

600

rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),

sys/arm64/nvidia/tegra210/max77620_gpio.c

649

rv = RM1(sc, sc->gpio_pins[pin]->reg, MAX77620_REG_GPIO_OUTPUT_VAL(~0),

sys/arm64/nvidia/tegra210/max77620_regulators.c

384

rv = RM1(sc->base_sc, sc->def->volt_reg,

sys/arm64/nvidia/tegra210/max77620_regulators.c

413

rv = RM1(sc->base_sc, sc->def->fps_reg, MAX77620_FPS_SRC_MASK,

sys/arm64/nvidia/tegra210/max77620_regulators.c

448

rv = RM1(sc->base_sc, sc->def->fps_reg, mask, val);

sys/arm64/nvidia/tegra210/max77620_regulators.c

473

rv = RM1(sc->base_sc, sc->def->pwr_mode_reg, sc->def->pwr_mode_shift,

sys/arm64/nvidia/tegra210/max77620_regulators.c

538

rv = RM1(sc->base_sc, sc->def->cfg_reg, mask, val);

sys/dev/iicbus/pmic/act8846_regulator.c

261

rv = RM1(sc->base_sc, sc->def->voltage_reg,

sys/dev/iicbus/pmic/act8846_regulator.c

285

rv = RM1(sc->base_sc, sc->def->enable_reg,